Ultra-thin gate oxide formation using an N2O plasma

Details Ultra-thin gate oxide formation using an N2O plasma Ultra-thin gate oxide formation using an N2O plasma

1999-02-09

2001-07-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S513000

Reexamination Certificate

active

06258730

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to fabrication of integrated circuits, and more particularly to a controllable and reproducible method for growing an ultra-thin gate oxide by directly reacting an N
2
O plasma with a silicon substrate.
2. Description of the Related Art
MOSFETs (metal-oxide-semiconductor-field-effect transistors) are the basic building blocks of modem integrated circuits. The conventional fabrication of MOSFET devices is well known. Typically, MOSFETs are manufactured by depositing an undoped polycrystalline silicon (“polysilicon”) material over a gate oxide layer arranged above a semiconductor substrate. The polysilicon material and the gate oxide layer are patterned to form a gate conductor arranged between a source region and a drain region. The gate conductor and source/drain regions are then implanted with an impurity dopant. If the dopant species employed for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (n-channel) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (p-channel) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
As MOSFET feature sizes decrease, gate oxide thickness decreases as well. This decrease in gate oxide thickness is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET sub-threshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts.
Another factor driving reduction of gate oxide thickness is the increased transistor drain current realized for a reduced gate dielectric thickness. Higher transistor drain currents are desirable because they allow each transistor to drive a greater number of other transistors, and can result in increased switching speeds. The transistor drain current is proportional to the amount of charge induced in the transistor channel region by the voltage applied to the gate conductor. The amount of charge induced by a given voltage drop across the gate oxide is the voltage drop multiplied by the capacitance of the oxide. Increasing the capacitance of the oxide therefore increases the transistor drain current. The capacitance C of the oxide can be written as for a parallel plate capacitor:
C=&egr;A/t
ox
,
where &egr; is the permittivity of the oxide, A is its area, and t
ox
is the oxide thickness. It can be seen that reducing oxide thickness increases the oxide capacitance and thereby the drive current of a transistor.
A gate oxide is typically grown onto the upper surface of a silicon substrate by heating the substrate to a temperature greater than about 700° C. in an oxidizing ambient. Such thermal oxides have been traditionally preferred over deposited oxides because thermal oxides generally exhibit lower trap state densities within the oxide and at the silicon/oxide interface. Trap states are energy levels, typically associated with impurities or defects, that can trap electrons or holes at the location of the impurity or defect. “Hot” carriers, or carriers that attain high kinetic energy (typically from the electric field moving them along a transistor channel), are particularly susceptible to being injected into the oxide and captured by trap states there. If a sufficiently high density of trap states is associated with an oxide, charge may build up in the oxide as carriers become trapped. This can lead to shifts in the transistor threshold voltage with time.
Although thermal oxides are attractive because of the low trap densities associated with them, growth of very thin thermal oxides (i.e., less than about 100 angstroms thick) does present difficulties. For example, the growth rate of a thermal oxide is dependent on oxide thickness for a given set of growth conditions. In particular, the growth rate is more rapid during the initial stages of growth than it is after growth of approximately 300 angstroms of oxide. Initial-stage oxide growth can be modeled using a growth rate that decreases exponentially with increasing thickness. This strong variation of growth rate for low oxide thicknesses makes it difficult to grow controllable, reproducible oxides with thicknesses of less than about 50 angstroms. Another problem associated with a strongly varying growth rate is an inability to produce highly uniform gate oxide thicknesses (i.e., less than 1% standard deviation).
Yet another problem with growing very thin oxides is that roughness, contamination, and imperfections in the starting silicon surface become increasingly important to the integrity of the grown oxide. Any locally weak or excessively thin spots may become preferred sites for breakdown of the oxide when exposed to electric fields during device operation. Breakdown is a potential problem with very thin oxides, whether they are grown or deposited, and may be precipitated by physical defects such as pinholes or thin areas. Trap states within the oxide may also lead to breakdown, by trapping charge, which causes locally elevated electric fields. Tunneling current through the oxide may be locally increased as a result of such an elevated field, leading to breakdown.
It would therefore be desirable to develop a method for controllable, reproducible formation of uniform, ultra-thin (less than about 20 Å thick) gate oxides. The desired gate oxide should be breakdown-resistant and substantially free of trap states that may cause V
T
shifts.
SUMMARY OF THE INVENTION
The problems outlined above are overcome by subjecting a silicon substrate to an N
2
O plasma to form an ultra-thin gate oxide. By reacting an N
2
O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 Å and relative thickness uniformities of less than 1% standard deviation (measured as a percentage of the oxide thickness). A subsequent high temperature anneal may then be performed to reduce the density of trapping states. In this manner, the disclosed method offers a means for controllably and reproducibly forming uniform, ultra-thin gate oxides that are resistant to breakdown.
Broadly speaking, a method is contemplated for forming an ultra-thin gate oxide by reacting an N
2
O plasma directly with a silicon substrate. A silicon substrate is provided, which preferably includes monocrystalline silicon. An RCA cleaning may be performed to reduce roughness, imperfections, and contaminants that may be present in the surface of the silicon substrate. In addition, a cleaning may be advantageously employed to remove any native oxide layer that may have formed upon the silicon substrate. According to an embodiment, formation of an ultra-thin gate oxide includes placing the silicon substrate into a reaction chamber, ideally a deposition chamber of a type used in plasma enhanced chemical vapor deposition (PECVD). The deposition temperature is preferably between about 350° C. and about 450° C., and more preferably between about 390° C. and about 410° C. Once the temperature in the deposition chamber reaches a desired level, N
2
O may be flowed above the silicon substrate, preferably through a showerhead positioned above the silicon substrate. The N
2
O flow rate is preferably between about 600 sccm and about 800 sccm, and the chamber pressure is preferably between about 2.2 torr and about 2.6 to

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