Ultra-thin body super-steep retrograde well (SSRW) FET devices

Details Ultra-thin body super-steep retrograde well (SSRW) FET devices Ultra-thin body super-steep retrograde well (SSRW) FET devices

2006-02-21

2006-02-21

Owens, Douglas W (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C438S153000, C438S154000

Reexamination Certificate

active

07002214

ABSTRACT:
A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

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