Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-07-22
2000-07-18
Elms, Richard T.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438585, 438197, 438299, H01L 21336
Patent
active
060906723
ABSTRACT:
This invention is a damascene processing method for forming ultra short channel MOS transistors, where the channel length is not determined by photolithography. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the MOS channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to the MOS gate electrodes directly over channel regions, and allows borderless connections to be made to the MOS source and drain regions, thereby improving layout density of small transistors. The method uses metal for first level interconnect lines rather than polysilicon. The method enables the interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon substrate. The method also prevents plasma damage of very thin gate dielectrics during processing.
REFERENCES:
patent: 5960270 (1999-09-01), Misra et al.
Elms Richard T.
Smith Brad
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