Ultra-shallow semiconductor junction formation

Details Ultra-shallow semiconductor junction formation Ultra-shallow semiconductor junction formation

2001-06-11

2003-03-25

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S474000, C438S231000, C438S232000

Reexamination Certificate

active

06537886

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to microelectronics and, in particular, to a method of fabricating an ultra-shallow junction in Field Effect Transistor (FET) devices, such as Complementary Metal Oxide Semiconductor (CMOS) devices.
BACKGROUND OF THE INVENTION
Advances in the miniaturization of CMOS devices have been a key driving force behind the explosive growth of various network centric computing products such as ASIC high speed microprocessors and memories, low power hand-held computing devices, cable modems and advanced multi-media audio and video devices. Smaller CMOS devices typically equate to faster switching times which led to speedier and better performing end user systems.
The process of miniaturizing CMOS devices involves scaling down various horizontal and vertical dimensions in the CMOS device structure. In particular, the thickness of the ion implanted source/drain junction of a p- or n-type transistor is scaled down with a corresponding scaled increase in the substrate channel doping. In this manner, constant electric field is maintained in the transistor channel which results in higher speed performance for the scaled down CMOS transistor. For example, for a 0.1 &mgr;m CMOS device, the source/drain extension junction closest to the transistor channel is as shallow as 50 nm and has a channel doping concentration as high as 1×10
18
/cm
3
.
For CMOS devices with a critical gate dimension below 0.25 &mgr;m, a shallow junction is not the only requirement. A more important requirement, in the source/drain extension junction, is the abruptness of the junction/dopant profile slope which is in proximity to the transistor channel. As shown in FIG.
1
(
a
), there is more penetration of the source/drain dopant into the transistor channel as the junction/profile slope becomes less abrupt. This results in poor threshold voltage roll-off characteristics for sub-quarter micron CMOS devices (See, for example, FIG.
1
(
b
)). Thus, for small advanced CMOS devices, it is vital for the source/drain extension junction profile to be shallow, abrupt and have a high surface concentration.
The formation of source/drain extension junctions in CMOS devices is commonly carried out in the prior art by ion implantation in appropriately masked source/drain regions of a silicon substrate with boron (p-type) or arsenic and phosphorous (n-type) dopants. To minimize ion channeling during ion implantation, which will broaden the implanted profile, the silicon substrate is usually preamorphized with heavy ions such as Ge or Si. Preamorphization of silicon is a process in which sufficient ion dose is used to convert the surface region of the Si substrate from crystalline to amorphous. The depth of the converted amorphous region depends on the nature of the ions, ion energy and the dose of the incident ions on the silicon substrate. Although the preamorphization process helps to sharpen the implanted profile and improve the epitaxial silicon regrowth process during subsequent thermal annealing, it also creates extensive crystal damage and excess Si interstitials at the End of Range (EOR) of the preamorphized ions. As is known to those skilled in the art, Si interstitials are displaced Si atoms created by ion bombardment of the crystalline Si substrate. During thermal annealing, the presence of these EORs is detrimental since excess Si interstitials greatly enhance (10 to 1000 times) the normal diffusion of dopants through the Si substrate and result in a much deeper source/drain junction and poorer junction profile.
This greatly enhanced diffusion of dopants due to the presence of excess Si interstitials around the dopant atoms is commonly referred to in the prior art as transient enhanced diffusion (TED). In particular, the relatively high diffusivity of small boron dopants in combination with ion channeling and transient diffusion makes the fabrication of small p-type CMOS devices difficult. The aforementioned combination also represents a major hurdle that needs to be overcome before further miniaturization of the CMOS device technology can occur.
Several prior art approaches have attempted to reduce the transient enhanced diffusion for shallow junction formation. In one approach, a carbon co-implant was used to reduce the transient diffusion of boron dopant during rapid thermal anneal (RTA). The conditions employed in forming the shallow junction using carbon co-implantation were as follows: 2 keV boron shallow implant, dose 1×10
15
/cm
2
, carbon implant (energy not reported), dose=2×10
14
/cm
2
. Rapid thermal anneal (RTA) conditions were 950° C., 30 seconds, or 1050° C., 30 seconds, respectively. Although carbon co-implant is effective in reducing the transient diffusion of boron, this method suffers from the disadvantage that high density of residual defects remain after RTA. This is the case even using high temperature anneal conditions (1050° C., 30 seconds). The high density of residual defects results in high electrical leakages for the shallow junction.
Another approach reported by T. H. Huang et al. (“Influence of Fluorine Preamorphization on the Diffusion and Activation of Low-energy Implanted Boron during Rapid Thermal Anneal,”
Appl. Phys. Lett.
, (1994) Vol. 65, No. 14, p. 1829) used fluorine co-implants to reduce the transient diffusion of boron dopants during rapid thermal anneals. The conditions used in this reference for shallow junction formation are as follows: fluorine implant, 40 keV ion energy, dose=2×10
15
/cm
2
, 5 keV boron or 23 keV BF
2
shallow implants. In the process disclosed by Huang et al., the wafers were rapid thermal annealed at 1000° C., 1050° C. and 1100° C. for 30 seconds. Although the presence of fluorine implants reduced the transient boron enhanced diffusion during RTA, this prior art method also suffers from the disadvantage that residual defects remain after 1000° C., 30 seconds anneal. Residual defects can only be removed with 1100° C., 30 seconds anneal. However, substantial dopant motion occurs at this higher temperature and therefor ultra-shallow junctions cannot be formed.
Another approach reported by S. Saito entitled “Defect Reduction by MeV Ion Implantation for Shallow Junction Formation,”
Appl. Phys. Lett.
, (1993) Vol. 63, No. 2, p. 197 used fluorine implants for preamphorization (40 kev, 1×10
15
/cm
2
), shallow implant; boron at 10 keV and 5×10
15
/cm
2
. This was followed by ion implantation of either fluorine or silicon at 1 MeV energy or arsenic at 2 MeV energy. The dose used for the MeV implant was between 5×10
14
to 5×10
15
/cm
2
. The samples were rapid thermal annealed at 1000° C. or 1100° C. for 110 seconds. Under these experimental conditions, Saito demonstrated that the MeV implants were effective in reducing the boron transient diffusion with and without fluorine preamphorization. This reference also demonstrated that maximum reduction in boron dopant diffusion was achieved when both fluorine preamorphization and Mev fluorine implants were used. However, as mentioned in the prior art earlier, use of fluorine implants creates residual defects and requires temperatures as high as 1100° C. for low leakage junction to be formed.
In each of the prior art references mentioned hereinabove, high energies were used to implant boron (2 to 10 keV) or BF
2
(23 keV) into semiconductor materials. These energy ranges are however unsuitable to create an ultra-shallow boron dopant junction below 50 nm. All the junction depths created by the prior art techniques are between 60-100 nm. Although the combination of high temperature (>1000° C.) and long annealing times (10 to 30 seconds) minimize residue defects due to carbon or fluorine co-implants, it inhibits the formation of ultra-shallow junctions. Moreover, all of the prior art techniques overlook the importance of the rate at which the wafer reaches the desired anneal temperature, i.e., 1000° to 1100° C., as well as ramp down rate for the wafer to cool down from the anneal temperature. Despite the curre

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