Ultra-shallow semiconductor junction formation

Details Ultra-shallow semiconductor junction formation Ultra-shallow semiconductor junction formation

1998-05-12

2000-03-14

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257345, H01L 2976

Patent

active

060376406

ABSTRACT:
A method for fabricating an ultra-shallow semi-conductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

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patent: 5895954 (1999-04-01), Yasumura et al.
patent: 5897363 (1999-04-01), Gonzalez et al.
1. T. H. Huang, et al., "Influence of Fluorine Preamorphization on the Diffusion and Activation of Low-Energy Implanted Boron During Rapid Thermal Annealing," Appl. Phys. Lett., vol. 65, No. 14, pp. 1829-1831 (1994).
2. S. Saito, et al., "Defect Reduction by MeV Ion Implanation for Shallow Junction Formation," Appl. Phys. Lett., vol. 63, No. 2, pp. 197-199 (1993).
3. Somnath Nag, et al., "Shallow Trench Isolation for Sub-0.25-um IC Technologies," Solid State Technology, pp. 129-136, (1997).

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