Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-10-24
2010-06-01
Nguyen, Ha Tran T (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S249000, C438S392000, C438S358000, C438S369000, C257SE21211, C257SE21466, C257SE21468
Reexamination Certificate
active
07727845
ABSTRACT:
An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.
REFERENCES:
patent: 2001/0039094 (2001-11-01), Wristers et al.
patent: 2004/0072446 (2004-04-01), Liu et al.
patent: 2005/0093075 (2005-05-01), Bentum et al.
Huang Yi-Chun
Ting Steve Ming
Wang Chih-Hao
Wang Yen-Ping
Brown Valerie
Nguyen Ha Tran T
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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