Ultra shallow extension formation using disposable spacers

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438305, H01L 21336

Patent

active

061272345

ABSTRACT:
The present invention is directed to a method of forming ultra shallow extensions in a transistor and a device incorporating same. The method comprises forming a gate dielectric and a gate conductor above a surface of a semiconducting substrate and forming a first plurality of sidewall spacers adjacent the gate dielectric and the gate conductor. The method continues with implanting the substrate with a dopant material to form a plurality of doped regions in the substrate, heating the substrate to drive the dopant material towards the gate dielectric, and removing the first plurality of sidewall spacers. The method further comprises forming a second plurality of sidewall spacers adjacent the gate dielectric and the gate conductor, and performing a second ion implantation process to complete the formation of source/drain regions in said substrate. The present invention is also directed to a structure comprising a gate dielectric positioned above a surface of a semiconducting substrate, and a gate conductor positioned above the gate dielectric. The structure further comprises a plurality of sidewall spacers positioned adjacent the gate dielectric and the gate conductor, the sidewall spacers having a certain thickness. The structure further comprises a plurality of doped regions formed in the substrate that are laterally spaced apart from the gate dielectric by an amount corresponding to the approximate thickness of the sidewall spacers.

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