Ultra low jitter differential to fullswing BiCMOS comparator wit

Details Ultra low jitter differential to fullswing BiCMOS comparator wit Ultra low jitter differential to fullswing BiCMOS comparator wit

1996-06-13

1999-05-04

Tokar, Michael

Electronic digital logic circuitry

Interface

Logic level shifting

326 77, 326 66, H03K 190175

Patent

active

059007460

ABSTRACT:
A pair of complementary signals are switched between a high state and a low state such that the complementary signals are switched within a time period less than two gate delays. An inverter biases other inverters so that these two inverters are maintained at their threshold levels. The maintenance at the threshold values enable these two inverters to be switched quickly.

REFERENCES:
patent: 5214317 (1993-05-01), Nguyen
patent: 5329183 (1994-07-01), Tamegaya
patent: 5465057 (1995-11-01), Takahashi
patent: 5528171 (1996-06-01), Doi et al.
patent: 5534794 (1996-07-01), Moreland
patent: 5631580 (1997-05-01), Rau

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