Ultra high density NOR gate using a stacked transistor arrangeme

Details Ultra high density NOR gate using a stacked transistor arrangeme Ultra high density NOR gate using a stacked transistor arrangeme

1996-11-07

1998-11-10

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438306, H01L 21336

Patent

active

058343547

ABSTRACT:
A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allow development of a high density NOR gate. The NOR gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

REFERENCES:
patent: 5624862 (1997-04-01), An
patent: 5714394 (1998-02-01), Kadosh et al.

Affiliated with

Also associated with

Rating

Ultra high density NOR gate using a stacked transistor arrangeme does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ultra high density NOR gate using a stacked transistor arrangeme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra high density NOR gate using a stacked transistor arrangeme will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1516215