Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-25
2001-04-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000
Reexamination Certificate
active
06211015
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits, and particularly to ultra high density flash memory having vertically stacked devices.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read only memories (EEPROMs) are reprogrammable nonvolatile memories that are widely used in computer systems for storing data both when power is supplied or removed. The typical data storage element of an EEPROM is a floating gate transistor, which is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions. Data is represented by charge stored on the floating gate and the resulting conductivity obtained between source/drain regions.
Increasing the storage capacity of EEPROM memories requires a reduction in the size of the floating gate transistors and other EEPROM components in order to increase the EEPROM's density. However, memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication. For example, the present generation of high density dynamic random access memories (DRAMs), which are capable of storing 256 Megabits of data, require an area of 8 F
2
per bit of data. There is a need in the art to provide even higher density memories in order to further increase storage capacity.
SUMMARY OF THE INVENTION
Embodiments of the present invention include an ultra high density electrically erasable and programmable read only memory (EEPROM) providing increased nonvolatile storage capacity through the use of vertically stacked devices. In one embodiment, the memory allows simultaneous erasure of multiple data bits, and is referred to as a flash EEPROM. Both bulk semiconductor and semiconductor-on-insulator (SOI) embodiments are included. Embodiments of the present invention includes bulk semiconductor and semiconductor-on-insulator ultra high density flash EEPROM having increased nonvolatile storage capacity. If a floating gate transistor is used to store a single bit of data, an area of only F
2
is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F
2
is needed per bit of data. The increased storage capacity of the flash EEPROM is particularly advantageous in replacing hard disk drive data storage in computer systems. In such an application, the delicate mechanical components included in the hard disk drive are replaced by rugged, small, and durable solid-state flash EEPROM packages. The flash EEPROMs provide improved performance, extended rewrite cycles, increased reliability, lower power consumption, and improved portability.
In one embodiment of the invention, a memory cell includes a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The pillar includes source/drain and body regions and has a number of sides. A pair of vertically stacked floating gates is included on at least one of two sides of the pillar. A control gate line also passes through each memory cell. Each memory cell is associated with a control gate line so as to allow selective storage and retrieval of data on the floating gates of the cell. In one embodiment, the control gate line is capable of storing more than two charge states on its associated floating gate.
Other embodiments of the present invention include memory cells, devices, arrays, and methods of making such arrays, all of which utilize vertically stacked devices. Still further and other embodiments, advantages and aspects of the invention will become apparent by reading the following detailed description, and by reference to the drawings.
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Booth Richard
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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