Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2002-09-30
2003-09-09
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S126000, C438S127000, C438S106000
Reexamination Certificate
active
06617201
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor fabrication. More particularly, the present invention relates to the fabrication of BOC (Board-on-Chip) FBGA (fine-pitch ball grid array) packages.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled circuits are used in a wide variety of applications. Such applications include personal computers, control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device coupled to the microprocessor. Devices such as these are formed from a plurality of electrical circuits placed together in what is known in the art as a package. The packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Many electrical circuits are packaged for surface mounting, and Fine-Pitch Surface Mount Technology (FPT) and Pin Grid Array (PGA) technology are well developed areas of this type of packaging technology. In addition, an emerging packaging method has been developed using Ball Grid Array (BGA) technology.
BGA technology offers several advantages over FPT and PGA. Among the most often cited advantages of BGA are: reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multilayer interconnect options; higher I/Os for a given footprint; easier extension to multichip modules; and faster design-to-production cycle time.
While BGA technology provides many benefits, there is still a growing demand for more component functionality in a smaller space. Despite the benefits provided by BGA technology, BGA is still a surface mount technology like FPT and PGA and, thus, is limited by the space available on the mounting surface. Significant research and development has been devoted to finding ways to get more and more capabilities into smaller areas. Engineers have been challenged with finding ways to increase hardware capabilities, with memory capacity being one area in which board geography is at a particular premium is memory. However, regardless of whether FPT, PGA or BGA is implemented, surface mount technologies are limited by the space available on the ceramic substrate or printed circuit board (PCB). As a result, the amount of memory will disadvantageously be limited by the dimensions of the mounting surface.
An advance in BGA array technology has been found in the reduction of ball pitch used in forming the arrays. This technology, known as Fine-Pitch ball Grid Array (FBGA), allows for a smaller footprint and higher density of electrical connections than does conventional BGA technology. For example, in one instance a conventional BGA device measures 35 mm square and contains 352 balls or bumps in the array, this is compared to a similar device made using FBGA technology which measures 21 mm square and contains 400 balls in the array.
In forming BGA and FBGA packages, one important step is that of encapsulating the microchip or die and substrate. Proper flow of the encapsulating material is required to obtain maximum uniformity in the resultant characteristics of the molded encapsulating material. Non-uniform material characteristics in the molded encapsulating material can create undesired stresses resulting in cracking of the encapsulating body. Other harmful effects of improper molding techniques include delamination of the molded encapsulating material and bridging of electrical pathways. Thus the encapsulating process plays an important role in formation of BGA and FBGA packaged devices.
The present invention may address one or more of the problems set forth above.
SUMMARY OF THE INVENTION
Certain aspects commensurate in scope with the originally claim invention are set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of certain forms the invention might take and that these aspects are not intended to limit the scope of the invention. Indeed, the invention may encompass a variety of aspects that may not be set forth below.
In accordance with one aspect of the present invention, an FBGA packaged device is provided. The package includes a die adhered to a substrate with a small gap being formed between the die and substrate. An opening, or a channel, is formed through the substrate adjacent the center portion of the die. An encapsulating mold is formed around the die, extending into the gap and also filling the channel. At least one barrier is disposed between the substrate and the die adjacent the channel to control the flow path of the encapsulating material, or molding compound, as the mold is formed in the package.
The present invention also provides a method for forming an encapsulated BGA or FBGA device allowing for improved moldability in the encapsulated package. The method provides for strategically placing a barrier between a die and a substrate to control the flow of molding compound thus producing more uniform material characteristics and fewer defects in the resultant mold.
REFERENCES:
patent: 6281044 (2001-08-01), VanNortwick
patent: 6473311 (2002-10-01), James et al.
patent: 2001/0038141 (2001-11-01), Wensel
patent: 2002/0016023 (2002-02-01), Bolken
patent: 6-232195 (1994-08-01), None
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Chye Lim T.
Guay Patrick
Kuan Lee C.
Teoh Tim
Toh Jeffrey
Fletcher Yoder & Van Someren
Micro)n Technology, Inc.
Talbott David L.
Thai Luan
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