U-gate transistors and methods of fabrication

Details U-gate transistors and methods of fabrication U-gate transistors and methods of fabrication

2006-07-04

2006-07-04

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S284000, C257S365000, C257S401000, C257S623000

Reexamination Certificate

active

07071064

ABSTRACT:
A process is described for manufacturing of non-planar multi-corner transistor structures. A fin of a semiconductor material having a mask on a top surface of the fin is formed on a first insulating layer. A second insulating layer is formed on the fin exposing a top surface of the mask, wherein a protection layer is deposited between the fin and the second insulating layer. Next, the mask is removed and spacers are formed on the fin adjacent to the protection layer. A recess having a bottom and opposing sidewalls is formed in the fin. A gate dielectric layer and a gate electrode are formed on the top surface, the opposing sidewalls of the fin and on the bottom and on the opposing sidewalls of the recess in the fin. A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.

REFERENCES:
patent: 6475890 (2002-11-01), Yu
patent: 6562665 (2003-05-01), Yu
patent: 2005/0035391 (2005-02-01), Lee et al.
patent: 2005/0104096 (2005-05-01), Lee et al.

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