Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-21
2001-05-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000
Reexamination Certificate
active
06235592
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention generally relates to a method of fabrication of Mask ROM, and more precisely to a method of fabrication of new type of Trench Mask ROM.
2. Background of the Related Art
As the complexity and performance of ICs increase, more processing steps are needed to fabricate them. Four or five mask levels were quite adequate for primitive ICs in the 1970s, whereas 16-Mb (ultra large-scale integration or ULSI) memory chips require more than twenty mask levels. For bit densities of up to one megabit, planartype storage capacitors are used.
Read Only Memory is so named because its cells can read data only from the memory cells. The ROM can be distinguished as Mask ROM, PROM (Programmable ROM), EPROM (Erasable Programmable ROM) and EEPROM (Electrically Erasable Programmable ROM) depending on the particular method a ROM uses to store data. The Mask ROM is most fundamental ROM.
The fabrication of a typical planar type of Mask ROM is described as follows. The description of the process sequence for forming a planar type of Mask ROM is as shown in
FIG. 1
a
to
FIG. 1
e.
Referring first to
FIG. 1
a,
a portion of the substrate
100
lightly with p-type dopant is shown. Furthermore, there are field-oxide areas
106
on both sides of the top portion of the substrate
100
. A photo resist
104
is formed on the outer surface of the substrate
100
to define plural doped regions
102
. The plural doped regions
102
are formed using an ion-implanting technique, wherein the plural doped regions
102
are implanted with n
+
-type ion, such as As or P. The photo resist
104
is removed and the photo resist
104
is used to define the doped regions
102
. Referring to
FIG. 1
b
, after removing the photo resists
104
boron ions are implanted into the substrate to form cell isolation region
108
. The cell isolation region
24
is used for suppressing the leakage. Referring to
FIG. 1
c,
a gate oxide layer
110
is formed on the substrate
100
and the doped regions
102
. And, a polysilicon layer
112
is formed sequentially on the gate oxide layer
110
.
Referring to
FIG. 1
d,
a photo mask
114
is used during a boron ion-implanting step, wherein the photo mask
114
is used to define a coding cell for forming a Mask ROM. Then, a Mask ROM is formed with some high-logic-level regions. As shown in
FIG. 1
e
, there is a fixed threshold voltage between two adjacent doped regions
102
. According to the doped regions
102
doped with n
+
-type dopant and the doped regions
116
doped with boron ions will increase the threshold voltage. Namely, a higher threshold voltage relates to a high-logic-level. Conversely, a low-logic-level is one pair of two the adjacent doped regions
102
which contains an undoped region
118
between the two adjacent doped regions
102
.
However, as component density has increased, the amount of charge need for a sufficient noise margin remains fixed. And, a device is composed of huge number of components. Further, a chip contains a lot of devices. As described above, the typical planar type of Mask ROM cannot satisfy the reduction of the device scale. Hence, it is difficult to compose a huge number of devices on a small chip. Furthermore, as the size of device is reduced the distance between two adjacent components is so close so as to cause the current leakage on the surface of the device. Hence, the current leakage and small-scale integration lead the fabrication of the mask ROM to be restricted. Therefore, in order to reduce leakage and cell size and to form large-scale integration, a new type of Trench Mask ROM cell is needed.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a new type of Trench Mask ROM cell and fabricating method for such a cell. The Trench Mask ROM cell can achieve purposes such as forming a large-scale integration and reducing current leakage and the size of device.
Briefly described, the present invention relates to a method for fabricating a Trench Mask ROM cell. An embodiment of the method comprises the following steps. For simplification, an example is used to describe the present invention. First, a p-well with p-type dopant on p-type substrate or n-type substrate is provided. A pad oxide layer and a first nitride layer are formed sequentially on the substrate. Plural trenches are formed using well-known etching techniques. After etching back the first nitride layer and the pad oxide layer, the plural trenches are formed on the substrate. Then, a gate oxide layer is formed on the surface of each trench by using either a thermal oxidation or a deposition technique. After the gate oxide layer is formed, the first nitride layer is removed. And, n
+
-type ions are implanted into the substrate below the pad oxide layer between each of the two trenches and the gate oxide layer on the bottom of each trench. Such n
+
-type ions are arsenic or phosphoric ions. A second nitride layer is formed on the outer surface on the substrate. Further, each trench is filled with oxide. After filling the oxide, the surfaces are etched and processed using chemical-mechanical polishing or etch back technique and stop on the nitride layer on the pad oxide. After that, a photo resist is formed to define a coding of the Trench Mask ROM. Namely, using the photo resist exposes some of the trenches. By using the etching technique, the filled-oxide and the nitride layer of the exposed trenches are removed. Sequentially, the photo resist is removed after the etching step. Finally, a polysilicon layer is formed on the nitride layer on the pad oxide layer, filled-oxide in the trenches and the gate oxide on the bottom of trenches. The polysilicon is patterned to define as word line of the Trench Mask ROM.
The Trench Mask ROM includes low-logic-level regions and high-logic-level regions. And, the low-logic-level regions are referred to as those regions having low threshold voltage. Conversely, the high-logic-level regions are referred to those regions having high threshold voltage. The threshold voltage between two adjacent stacks is depended on the depth and the conductivity of the trench between the two stacks. The threshold voltage is increased if the depth of the trench become deeper. Otherwise, the threshold voltage is increased gain if the trench is filled with oxide. And, the high threshold voltage and low threshold voltage are respectively to “off ” state and “on” state. Thus, the Trench Mask ROM is coded.
By using these methods, the purposes of forming a large-scale integration, suppressing current leakage and reducing of the size of the device can be achieved.
REFERENCES:
patent: 5904526 (1999-05-01), Wen et al.
patent: 5937280 (1999-08-01), Wen
Mosel Vitelic Inc.
Nelms David
Vu David
LandOfFree
Type of high density vertical Mask ROM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Type of high density vertical Mask ROM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Type of high density vertical Mask ROM cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2551022