Two-step planarization process using chemical-mechanical polishi

Details Two-step planarization process using chemical-mechanical polishi Two-step planarization process using chemical-mechanical polishi

1996-09-24

1998-05-05

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438633, 438699, H01L 21316

Patent

active

057473820

ABSTRACT:
A novel method is presented to form and planarize an inter-metal-dielectric(IMD) layer of an integrated circuit with two or more levels of interconnection metallurgy. The method utilizes chemical-mechanical-polishing(CMP) followed by reactive-ion-etching(RIE) to first planarize and then etch back a deposited IMD layer. Metal line spacings of less than 1.5 microns produce voids in the IMD even when spin-on-glass(SOG) is used to partially fill the spaces prior to IMD deposition. These voids, which contain organic residues and debris, can produce eruptions of material during several subsequent processing steps. The method of this invention attenuates and de-activates these voids, rendering them completely benign. Since CMP is only used to achieve a planar surface, risks of CMP damage to alignment marks and other features are also reduced.

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