Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reissue Patent
2006-06-13
2006-06-13
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S648000, C438S672000
Reissue Patent
active
RE039126
ABSTRACT:
A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is more even with the insulation layer surface than conventional plug formation techniques. Conventional processes result in recessed plugs which are not easily or reliably coupled with subsequent layers of sputtered aluminum or other conductors. The inventive process uses a two-step chemical mechanical planarization technique. An insulation layer with contact holes is formed, and a metal layer is formed thereover. A polishing pad rotates against the wafer surface while a slurry selective to the metal removes the metal overlying the wafer surface, and also recesses the metal within the contact holes due to the chemical nature and fibrous element of the polishing pad. A second CMP step uses a slurry having an acid or base selective to the insulation material to remove the insulator from around the metal. The slurry also contains abrasive materials which polish the metal surface so as to make the metal level with the insulation layer surface. Removal of the insulation material can continue, thereby producing a slightly protruding plug which results in a more reliable contact from the substrate to subsequent conductive layers.
REFERENCES:
patent: 3841031 (1974-10-01), Walsh
patent: 4193226 (1980-03-01), Gill, Jr. et al.
patent: 4714686 (1987-12-01), Sander et al.
patent: 4811522 (1989-03-01), Gill, Jr.
patent: 4936950 (1990-06-01), Doan et al.
patent: 4992135 (1991-02-01), Doan
patent: 5055426 (1991-10-01), Manning
patent: 5063175 (1991-11-01), Broadbent
patent: 5137597 (1992-08-01), Curry, II et al.
patent: 5152868 (1992-10-01), Schiltz et al.
patent: 5266446 (1993-11-01), Chang et al.
patent: RE34583 (1994-04-01), Grief et al.
patent: 239927 (1986-10-01), None
patent: 0 343 698 (1989-11-01), None
patent: 63-90838 (1988-04-01), None
patent: 01017879 (1989-01-01), None
patent: 2-42728 (1990-02-01), None
patent: 3-244130 (1991-10-01), None
J. J. Estabil et al., “Electromigration Improvements with Titanium Underlay and Overlay in Al(Cu) Metallurgy”, VMIC Conference, pp. 242-248, Jun. 11-12, 1991.
Ronald R. Uttecht et al., “A Four-Level-Metal Fully Planarized Interconnect Technology for Dense High Performance Logic and SRAM Applications”, VMIC Conference, pp. 20-26, Jun. 11-12, 1991.
“Advanced Metallization for ULSI Applications”, Proceedings of the Conference held Oct. 8-10, 1991.
S. Wolf, “4.4.11 Chemical-Mechanical Polishing,”Silicon Processing for the VLSI Era, vol. 2—Process Integration, pp. 238-239, 1990.
Doan Trung T.
Yu Chris C.
Micro)n Technology, Inc.
Pert Evan
TraskBritt
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