Two stage sensing for large static memory arrays

Details Two stage sensing for large static memory arrays Two stage sensing for large static memory arrays

1997-01-31

1998-05-12

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

327 57, G11C 700

Patent

active

057516480

ABSTRACT:
A two stage latch sensing circuit provides high performance at low power in static random access memory (SRAM) devices. The first stage takes the small signal development from the array bitlines which is passed to the sense latch through bit-switches and amplifies it. P-type field effect transistor (PFET) devices are used to drive a precharged high, low-signal swing read data bus. The second stage sense latch amplifies the signal from the read data bus, thereby providing a full level swing to the outputs.

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