Two-stage 8T SRAM cell design

Details Two-stage 8T SRAM cell design Two-stage 8T SRAM cell design

2008-10-27

2011-11-01

Nguyen, Tuan (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189090, C365S189190, C365S194000

Reexamination Certificate

active

08050082

ABSTRACT:
An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node.

REFERENCES:
patent: 6091626 (2000-07-01), Madan
patent: 7471544 (2008-12-01), Nakazato et al.
patent: 7821309 (2010-10-01), Lee
patent: 7869261 (2011-01-01), Ozawa

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