Radiation imagery chemistry: process – composition – or product th – Plural exposure steps
Reexamination Certificate
2001-06-25
2004-10-12
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Plural exposure steps
C430S396000, C430S005000
Reexamination Certificate
active
06803178
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to semiconductor device manufacturing and, more particularly, to photolithographically forming plural features using different illumination conditions.
Semiconductor devices having smaller and smaller features are approaching a limit in which such features may be formed by conventional photolithography methods. For example, conventional photolithography methods produce vias in an insulating layer, as illustrated
FIGS. 1A and 1B
. A positive photoresist layer
3
is formed over an insulating layer
1
in which it is desired to form a first and second via. A plurality of regions
5
A,
5
B,
5
C and
7
in the photoresist layer
3
are simultaneously exposed to actinic light
8
through openings
11
A,
11
B,
11
C and
13
in a single mask or reticle
9
, as illustrated in FIG.
1
A. The terms mask and reticle are used interchangeably, with the term reticle often applied to a mask used in step and repeat exposure systems. The exposed regions
5
A,
5
B,
5
C and
7
are then developed and removed, while unexposed regions
6
remain as shown in
FIG. 1B. A
gas or liquid etching medium is then supplied through the openings
5
A,
5
B,
5
C and
7
in the photoresist layer
3
to etch vias
15
A,
15
B,
15
C and
17
in layer
1
, as illustrated in FIG.
1
C.
However, as the density of the vias has increased and the size of the vias has decreased, diffraction effects often result in patterning errors. These errors result in via size or location that deviate from the desired size or location.
Furthermore, only certain values of exposure dose and defocus are allowed to form an exposed region in the photoresist layer within the allowed design parameters. A set of allowed exposure dose and defocus values that may be used in exposing a particular region is referred to as a process window.
It has been suggested that the process window
101
for exposing dense regions in a photoresist layer differs from the process window
103
for exposing isolated regions in the photoresist layer, as shown in FIG.
2
A. See A. R. Newreueher and C. A. Mack, SPIE Short Course Note SC102, “Optical Lithography Modeling”, Feb. 27, 2000. For large features to be exposed, there is a large overlap
105
between the windows
101
and
103
, as shown in FIG.
2
A. Therefore, in order to expose both dense and isolated regions, the corresponding value of exposure dose and defocus must be located in the overlap region
105
between the process windows
101
and
103
. For large features to be exposed, it is relatively easy to select appropriate values of exposure dose and defocus that fall into the large overlap region
105
, as shown in FIG.
2
A.
However, the overlap region
205
of process windows for exposing dense
201
and isolated
203
regions in a photoresist layer is relatively small for exposed features having a small size, as shown in FIG.
2
B. Region
207
of process window
201
and region
209
of process window
203
outside the overlap region
205
cannot be used when exposing both dense and isolated regions. Therefore, it is difficult to select the exposure conditions which are optimum for both small dense and isolated regions because the process window overlap
205
for exposing such regions is also small.
BRIEF SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a method of making plurality of features in a first layer, comprising forming a photoresist layer over the first layer, exposing dense regions in the photoresist layer through a first mask under a first set of illumination conditions, exposing at least one isolated region in the photoresist layer through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions, patterning the exposed photoresist layer, and patterning the first layer using the patterned photoresist layer as a mask.
According to another aspect of the present invention, there is provided a method of making a semiconductor device comprising forming a first layer of the semiconductor device, forming a photoresist layer over the first layer, exposing dense regions in the photoresist layer through a first mask using a first focus, exposing isolated regions in the photoresist layer through a second mask different from the first mask using a second focus different from the first focus, removing the exposed dense and isolated regions in the photoresist layer to form a patterned photoresist layer, and etching the first layer using the patterned photoresist layer as a mask.
According to another aspect of the present invention, there is provided a method of making a semiconductor device, comprising forming at least one semiconductor device on a substrate, forming a first insulating layer over the semiconductor device, forming a photoresist layer over the first insulating layer, and exposing dense regions in the photoresist layer through a first mask using a first focus. The method further comprises exposing isolated regions in the photoresist layer through a second mask different from the first mask using a second focus different from the first focus, removing the exposed dense and isolated regions in the photoresist layer to form dense and isolated openings in the photoresist layer, providing an etching gas or an etching liquid to the first insulating layer through the dense and the isolated openings in the photoresist layer to form a plurality of dense and isolated openings in the first insulating layer, and forming a conductive material in the dense and the isolated openings.
REFERENCES:
patent: 5563012 (1996-10-01), Neisser
patent: 6218089 (2001-04-01), Pierrat
patent: 6309800 (2001-10-01), Okamoto
patent: 6337162 (2002-01-01), Irie
patent: 6498105 (2002-12-01), Kim
patent: 2001/0036604 (2001-11-01), Kawashima
patent: 2001/0055733 (2001-12-01), Irie et al.
patent: 2002/0001758 (2002-01-01), Petersen et al.
patent: 2002/0094482 (2002-07-01), Mansfield et al.
J.N.Helbert and T.Daou, “Resist Technology—Dessign, Processing and Application”, in Handbook of VLSI Microlithography, ed. Helbert, Noyes Publication, NY-2001, pp. 74-188.
Bell Scott A.
Kim Hung-Eli
Lukanc Todd P.
Okoroanyanwu Uzodinma
Plat Marina V.
Foley & Lardner LLP
Huff Mark F.
Sagar Kripa
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