Twin well forming method for semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438420, 438527, H01L 21761

Patent

active

059857102

ABSTRACT:
A twin well forming method for a semiconductor device includes the steps of forming a first insulation layer on a semiconductor substrate, selectively etching the first insulation layer to obtain a first insulation layer pattern and a first buffer insulation, ion-implanting first impurities through the first buffer insulation layer into the semiconductor substrate, forming a second insulation layer on the first insulation layer pattern and the first buffer insulation layer, spreading a planarizing material on the second insulation layer and applying the planarizing material to an annealing treatment to obtain a planarizing material layer, etching back the planarizing material layer and the second insulation layer to expose an upper surface of the first insulation layer pattern, forming a second buffer insulation layer by partially etching the first insulation layer pattern, ion-implanting second impurities through the second buffer insulation layer into the semiconductor substrate, removing the second insulation layer, the first buffer insulation layer and the second buffer insulation layer, and annealing the semiconductor substrate. The method prevents the upper surface of the semiconductor substrate from being stepped or becoming uneven during the twin well formation, thereby improving a product reliability.

REFERENCES:
patent: 4584027 (1986-04-01), Metz, Jr. et al.
patent: 5252510 (1993-10-01), Lee et al.
patent: 5670395 (1997-09-01), Pan

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