Twin MONOS cell fabrication method and array organization

Details Twin MONOS cell fabrication method and array organization Twin MONOS cell fabrication method and array organization

2001-11-21

2003-03-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S954000

Reexamination Certificate

active

06531350

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The Invention relates to methods of fabricating high-density twin MONOS (Metal/polysilicon Oxide Nitride Oxide Silicon) memory devices integrating CMOS control logic, suitable for various architectures.
2. Description of Related Art
Twin MONOS structure was introduced in the U.S. Pat. No. 6,255,166 issued on Jul. 3, 2001 to Seiki Ogura, and a variation is taught in co-pending U.S. patent application Ser. No. 09/595,059 (Halo-99-002) to Ogura et al, filed on Jun. 16, 2000. U.S. Pat. Nos. 6,166,410 to Lin et al and U.S. Pat. No. 6,054,734 to Aozasa et al show MONOS cells with dual gates and integrated array and logic processes. U.S. Pat. Nos. 5,851,881 to Lin et al and 6,177,318 to Ogura et al show MONOS memory devices.
SUMMARY OF THE INVENTION
Presented in this invention is a fabricating method for high-density twin MONOS memory devices integrating CMOS logic transistors into various array formations. The invention consists of the following fabrication methods:
i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication.
ii) Twin MONOS array in which bit line crosses word gate line and control gate. The invention, comparing to co-pending patent application 09/595059 (Halo99-002) where bit line and control gate are perpendicular to word line, focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two control gates on both sidewalls of a shared select (word) gate. The method is applicable to a device with a flat channel and/or a device having a step channel under control gate.
iii) Twin MONOS array architecture in which the shared bit line in adjacent cells in ii) is separated by shallow trench isolation (STI) and featured with individual contact to bit by metal line. The fabrication method can utilize the method in ii). This is a derivative of ii).
iv) Twin MONOS architecture in which one side of bit line is parallel to word and control gate lines and the other side of bit line is perpendicular to word and control gate lines. The contact process for the bit line perpendicular to word and control gate utilizes salicided bit diffusion line or tungsten plugged line. This is another form of partial usage of this new concept of bit line perpendicular to control gate in (ii).
Two embodiments of the present invention are disclosed.
1) The unique features of the first embodiment are a salicided bit line, cap nitride on a memory gate, and field implant isolation without STI. The word line crosses the bit line and the control gate.
1-1) The memory gate image and the logic (peripheral) gate are defined by a critical mask, where feature size is the smallest provided by the lithography tool in use.
1-2) Memory gates with cap nitride and logic gates with no cap nitride are simultaneously formed by a reactive ion etch. To achieve this one time etch,
Gate stack structure prior to a mask process from top to bottom is: oxide
itride/polysilicon/gate oxide in the memory area and nitride/oxide/polysilicon/gate oxide in the logic area.
The resist image transfer RIE stops at the polysilicon surface. The resist is stripped and the hard mask (oxide) is used for the polysilicon RIE.
An etch rate requirement for each layer at polysilicon RIE process is: polysilicon~nitride>>oxide. This is achievable with an ambient of CF
4
/O
2
for the bulk etch and HBr/O
2
/Cl
2
for the end point etch.
1-3) A boundary of the memory area and the logic area is placed on the cap nitride at the memory side so as not to leave a polysilicon spacer on the logic side.
1-4) DSW (disposal side wall) process is implemented to achieve an ultra short channel impurity profile in the memory area. As an option, a half cut ONO composite layer is formed under the control gate utilizing DSW as an etching mask. The bottom oxide in the logic area used for DSW formation in the memory area is conserved and used as an etch stop layer to remove the sidewall polysilicon.
1-5) ISSG (in-situ steam generation) is used for an ONO composite layer formation. The bottom oxide growth with ISSG provides a much smaller bird's beak compared to a conventional thermal oxide growth under the word gate. This improves significantly the read current. ISSG grows oxide not only on silicon but also on nitride. The growth rate on nitride is 0.6 times that on single crystal silicon at 950 to 1000° C. Then the oxide grown on the cap nitride isolates it from a nitride film of the ONO composite layer. This provides better insulation between the word gate and the control gate as well as less concern about word line to word line shorts. A nitride of the ONO composite layer is deposited by CVD after NH
3
treatment at 850° C. ISSG is also used to grow a top oxide by oxidizing the nitride. Since the oxide layer formed by oxidation of nitride is better quality compared to a deposited CVD oxide film, memory retention time is improved as well as improving program/erase characteristics.
1-6) The vertical reactive etch of polysilicon to form the memory control gate must be subjected to a long RIE breakthrough of the ONO insulation into silicon. At the completion of memory fabrication, the insulator between the control gate and the word gate depends on the height. When the top of the control gate is higher than the boundary of nitride and polysilicon, the insulator thickness gets thinner while removing the cap nitride. Therefore, the top control gate polysilicon has to be lower than the adjacent word gate nitride boundary. The memory bit line and source/drain area are protected by resist etch back process to prevent the etch from breaking through to the substrate during the first half of the etch. The logic source/drain region is defined by using the polysilicon spacer formed during memory control gate formation. The polysilicon spacer in the logic area is removed by CDE after source/drain ion implantation.
1-7) ISSG oxidation follows to recover RIE damages in the ONO composite layer and turn the remaining ONO nitride to oxide in the logic area.
1-8) About 200 Angstroms of oxide is deposited prior to memory source/drain implant to prevention implantation damage of the ONO composite layer.
1-9) The memory bit line, the memory control gate, the logic gate, and the logic diffusion are salicided to-lower their resistances. About 30 to 40 nm of BPSG is deposited conformally to keep enough of an isolation gap between the memory control gate and the memory bit line. Using BARC (bottom anti-reflective coating) /resist etch back, the BPSG over the control gate is removed by a wet etch to expand an exposed area of the memory control gate. The salicidation area is defined by a subsequent oxide spacer etch.
1-10) About 5000 Angstroms of a thick oxide is deposited over the salicided structures. About 1500 to 2000 Angstroms of nitride is deposited and a dummy pattern is left in the logic area as an etch stop for CMP.
2) The second embodiment differs from the first embodiment in the following aspects: Polycide gate such as stack of Tungsten/Tungsten-nitride/polysilicon or polysilicon gate, cap nitride, STI isolation, local wiring (long contact) process, and self aligned contact and metal bit line. The bit line crosses the word line and control gate. Adjacent bits isolated by STI are alternately connected by the long contact or adjacent bits are connected on the rectangular STI mask.
2-1) STI image is printed as a line shape instead of a rectangular shape to free from corner rounding. The corners of the rectangular STI on a mask are rounded through a lithography process as shown in FIG.
6
A. It may generate additional leakage concerned with overlay misalignment as shown in
FIG. 6A-2
. In this invention, STI and active area are printed as line and space to avoid the leakage effect due to the corner rounding and overlay-misalignment. Adjacent four memory bits are connected to each other by a rectangular shape c

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