Twin-bit memory cell having shared word lines and shared...

Details Twin-bit memory cell having shared word lines and shared... Twin-bit memory cell having shared word lines and shared...

2001-12-04

2003-09-16

Le, Dung Anh (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S261000, C438S262000, C257S291000, C257S301000, C257S309000, C257S314000

Reexamination Certificate

active

06620683

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to an electrically erasable programmable read-only memory (EEPROM), and more particularly to a novel twin-bit EEPROM structure and a method of fabrication. Adjacent floating gates in an array of EEPROM cells share a common control gate and a common bit-line contact. This novel structure results in an EEPROM with reduced cell size, higher erase speeds, and non-critical alignment of the control gate over the floating gates. More specifically, the channel length of the control gate is independent on the overlap between the control gate and the floating gates.
(2) Description of the Prior Art
A typical prior-art EEPROM-type device consists in part of an array of memory cells. Each cell is composed of a single field effect transistor (FET) having a floating gate and a control gate. The floating gate and control gate are typically formed by patterning two conductively doped polysilicon layers, and the floating gate, as its name implies, is completely surrounded by an electrically isolating dielectric. In the array of cells the floating gates are formed over a thin oxide grown on the device areas of the FETs. A portion of this oxide serves as a tunnel oxide in which hot electrons are injected from each FET source area to charge the floating gate electrode. A thin interlevel dielectric insulating layer is formed on the floating gates. The control gates are formed on the dielectric insulating layer over the floating gates, and extend over the FET channel areas adjacent to the floating gates and drain areas. Each control gate is accessed by the peripheral circuits on the EEPROM chip via word lines that interconnect the FET control gates. The control gates and floating gates are capacitively coupled through the thin dielectric layer. Selected cells are then coded (programmed) by applying a sufficiently high voltage potential between the control gate and the FET source, resulting in the injection of hot channel electrons in the substrate through the thin tunnel oxide into the floating gate. Since the floating gate is well insulated, the accumulated charge is retained for an indefinite period of time thereby providing for an array of coded non-volatile memory (NVM) cells. The charge stored on the floating gate shifts the threshold voltage (V
t
) on the programmed (charged) FET, while the V
t
on the non-programmed (uncharged) FET is not shifted in value. For example, if the floating gate is formed on an N-channel FET, the V
t
on the programmed FET (negatively charged gate) is shifted to a higher positive voltage. When the memory cell on the EEPROM chip is selected by the addressed decode circuit on the periphery of the EEPROM chip, and a gate voltage (V
g
) is applied to the control gate having a value between the V
t
of the non-programmed and programmed FETs, the non-programmed FET turns on and the programmed FET does not. The conductive state (on or off) of the FET channel is then interpreted as digital binary ones or zeros. Typically these EEPROM cells are erased by applying a high voltage (about 12 to 14 volts) to the control gates while grounding the source lines to charge or discharge the floating gates by way of Fowler Nordheim tunneling.
Typical EEPROM voltages applied to the source line (SL), control gate (CG) and bit line (BL) (drain) for the program cycle are shown in row 1 of TABLE I. The EEPROM is read by selecting the desired cells (floating gates) and applying the voltages shown in row 2 of TABLE I, and sensing the currents or voltages on the bit line. Finally the programmed EEPROM can be erased by applying the voltages shown in row 3 and relying upon the Fowler Nordheim tunneling to charge or discharge the floating gate.
TABLE I
SL
FG
CG
BL
1.
PGM FG
12-14V
0 or 1
2-3V
GRND
2.
READ FG
 2-3V
0 or 1
2-3V
SENSE
3.
ERASE FG
GRND
0 or 1
14V
GRND
One method of making these EEPROMs is described in U.S. Pat. No. 5,714,412 to Liang et al. A split-floating gate is formed between the FET source and drain and a control gate is formed between the split-gates. The floating gate in each cell can be individually programmed to provide for multilevel storage. Another method is described in U.S. Pat. No. 6,151,248 to Harari et al. In this method the control gate or select gate is shared by adjacent floating gates having right and left steering gates. A second version of Harari's EEPROM using a dual floating gate EEPROM cell array is described U.S. Pat. No. 6,103,573. In U.S. Pat. No. 5,812,449 to Song, an EEPROM is described in which two floating gates are formed between the source area and drain area to provide a 4-numeration information device. And in U.S. Pat. No. 5,494,838 to Chang et al. an EEPROM memory device is described using sidewall spacer floating gates.
However, there is still a need in the semiconductor industry to make EEPROM devices having increased cell density, relaxed alignment tolerance, and a simpler and more cost-effective process.
SUMMARY OF THE INVENTION
A principal object of this invention is to provide an EEPROM cell structure having increased cell density.
Another object of this invention is to form these EEPROM cells having a common control gate between adjacent floating gates and having a common bit-line contact.
A further object of this invention is to provide a process and structure with relaxed overlay alignment between the floating gate and the control gate.
In accordance with the objectives of this invention, a method is provided for fabricating a novel electrically erasable and programmable read only memory (EEPROM) device. Each memory cell in the EEPROM utilizes a common control gate between a first and a second floating gate, and utilizes a common bit line to form a more compact cell area with higher erase speeds. The method also provides a process that relaxes the overlay alignment tolerance between the control gate and the under lying floating gates.
In summary, the method for making this array of novel EEPROM cells begins by providing a semiconductor substrate, preferably a P
−
doped single-crystal silicon having a <100> crystallographic orientation, and having an array of device areas. Continuing with the process, a tunnel oxide layer is formed on the substrate, for example by thermal oxidation. A first polysilicon layer is deposited by LPCVD and is doped with an N-type dopant, such as As or P. Conventional photo-lithographic techniques and anisotropic etching are used to pattern the first polysilicon layer to form a first and second floating gate in each device area of the array of device areas. Next, source areas are formed in the substrate adjacent to the outer edges of the pair of floating gates and a drain area is formed adjacent to and between the first and second floating gates. For example, the source and drain areas can be formed at the same time by ion implanting an N type dopant, such as arsenic. A conformal gate oxide layer is formed over the floating gates by a second thermal oxidation. A conformal second poly-silicon layer is deposited and doped with and N type dopant, such as phosphorus. The second polysilicon layer is patterned to form a control gate. A key feature of this invention is to provide a control gate over the drain area that also extends partially over the adjacent first and second floating gates. This partial overlay provides greater latitude in aligning the control gate over the floating gates. This invention also provides a novel structure by patterning the control gate to expose underlying portions of the drain area for a common bit-line contact in each cell area, which results in increased cell density. An interlevel dielectric (ILD) layer is deposited on the substrate to electrically insulate the floating gates and control gates from the next level of interconnections. The ILD layer is preferably a doped silicon oxide (SiO
x
) deposited by chemical vapor deposition (CVD). Contact openings are etched in the ILD layer, which include a contact opening to each drain area for a bit-line contact in each of the device

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