Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-02-14
2006-02-14
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S752000, C714S746000
Reexamination Certificate
active
07000169
ABSTRACT:
Provided are methods and apparatuses for decoding input data by using a single decoder for decoding a first set of symbols and then, after those decoded symbols have been interleaved, using the same decoder for decoding the decoded and interleaved first set of symbols together with a second set of symbols. Also provided are methods and apparatuses for decoding input data by using multiple read/write means for controlling the storage and reading of data so as to interleave and/or de-interleave data simultaneously with data buffering.
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Fung, Dr. Mike, “The Supertek S-1 Mini-Supercomputer”, Compcon Spring '88, Thirty-Third IEEE Computer Society International Conference, Digest of Papers, Feb. 29-Mar. 3, 1988, pp. 116-118, especially abstract and Supertek S-1 functional block diagram.
Gandhi, Dipakkumar B., Office Action in U.S. Appl. No. 09/668,059, mailed Jul. 21, 2003, pp. 1-8.
Gandhi Dipakkumar
Lamarre Guy
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
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