Turbo coding, decoding devices and turbo coding, decoding...

Details Turbo coding, decoding devices and turbo coding, decoding... Turbo coding, decoding devices and turbo coding, decoding...

1999-04-30

2001-05-15

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C375S265000

Reexamination Certificate

active

06233711

ABSTRACT:

TECHNICAL FIELD
This invention relates to turbo coding and decoding devices and turbo coding and decoding methods suitable for application to encoding and decoding of turbo codes employed in satellite communications or the like, for example.
BACKGROUND ART
A turbo code is known as a code indicative of the performance close to the Shannon limit corresponding to a theoretical limit of the code performance. As to the turbo code, coding is performed by a combination of a plurality of convolution coding circuits and interleave circuits (hereinafter called “interleavers”). On the decoding side, the transfer of information about input data is performed between decoding circuits for outputting a plurality of soft outputs thereby to obtain the final result of decoding.
FIG. 15
shows a configuration of a conventional turbo coding device
300
. The turbo coding device
300
has a convolution coding circuit
301
-
1
for performing convolutional coding on input data D
301
thereby to obtain coded data D
302
-
1
, interleavers
302
-
1
through
302
-(m−1) for successively interleaving the input data D
301
, and convolution coding circuits
301
-
2
through
301
-m for respectively performing convolutional coding on data outputted from these interleavers
302
-
1
through
302
-(m−1) thereby to obtain coded data D
302
-
2
through D
302
-m. Here, m is an integer greater than or equal to 2.
The convolution coding circuits
301
-
1
through
301
-m perform convolutional arithmetic operations on the input data and output the results of arithmetic operations as coded data, respectively. Further, the interleavers
302
-
1
through
302
-(m−1) interleave the sequence of respective data in the input data and output the so-processed data therefrom.
FIG. 16
shows one example of the convolution coding circuits
301
-
1
through
301
-m. The convolution coding circuit
310
shown in
FIG. 16
is a feedback type convolution coding circuit having a bound length
3
. This coding circuit
310
has two shift registers
311
-
1
and
311
-
2
, three exclusive OR circuits (hereinafter called “EXOR circuits”)
312
-
1
through
312
-
3
, and a termination circuit
313
, and generates coded data D
312
from input data D
311
.
Here, the shift registers
311
-
1
and
311
-
2
respectively serve as delay elements for delaying the input data by one unit time interval. Further, the EXOR circuits
312
-
1
through
312
-
3
output EXORing of the input data respectively. The termination circuit
313
outputs the input data D
311
until the coding of all the input data D
311
is brought to an end, and outputs feedback data D
313
by two unit time intervals (times corresponding to the number of shift registers) from the completion of the coding. Processing subsequent to the coding of all the input data D
311
is one for restoring all the contents of shift registers
311
-
1
and
311
-
2
to 0, which is called “termination”. On the decoding side, decoding is performed on the assumption of this processing.
FIG. 17
shows one example of the interleavers
302
-
1
through
302
-(m−1). The interleaver
320
shown in
FIG. 17
has an input data holding memory
321
, a data substitution circuit
322
, an output data holding memory
323
and a substitute data ROM (Read Only Memory)
324
, and interleaves the sequence of respective data related to input data D
321
thereby to obtain output data D
322
.
Here, the input data D
321
are temporarily stored in the input data holding memory
321
and thereafter the order of the data is re-arranged or sorted by the data substitution circuit
322
. The sorting of the sequence of the data is performed based on the contents of the substitute data ROM
324
, i.e., substitute position information. Each of the data whose sequence is sorted, are stored in the output data holding memory
323
from which they are thereafter outputted as the output data D
322
.
FIG. 18
shows an example of the operation of the interleaver
320
at the time that the size of the interleaver
320
is 5 and the contents of the substitute data ROM
324
are the ones shown in FIG.
19
. That is, when the input data D
321
are given as “11010”, “00111” is obtained as the output data D
322
.
The operation of the turbo coding device
300
shown in
FIG. 15
will be explained. The input data D
301
are supplied to the convolution coding circuit
301
-
1
. The convolution coding circuit
301
-
1
performs a convolutional arithmetic operation on the input data D
301
, followed by termination. Thus, the convolution coding circuit
301
-
1
outputs coded data D
302
-
1
obtained by a coding process including the termination.
The input data D
301
are supplied to a series circuit of the interleavers
302
-
1
through
302
-(m−1), where the sequence of the successively-input data are interleaved and the so-processed data are outputted. These output data of the interleavers
302
-
1
through
302
-(m−1) are respectively supplied to the convolution coding circuits
301
-
2
through
301
-m. The convolution coding circuits
301
-
2
through
301
-m respectively perform convolutional arithmetic operations on the output data of the interleavers
302
-
1
through
302
-(m−1), followed by termination, so that coded data D
302
-
2
through D
302
-m obtained by a coding process including the termination are outputted.
FIG. 20
shows the relationship between the numbers of bits for the input data D
301
and the coded data D
302
-
1
through D
302
-m employed in the turbo coding device
300
. The input k-bit data D
301
are subjected to coding processes including termination by the respective convolution coding circuits
301
-
1
through
301
-m and thereafter the so-processed respective data are outputted as (n
1
+t
1
) through (n
m
+t
m
)-bit coded data D
302
-
1
through D
302
-m.
FIG. 21
shows a configuration of a conventional turbo decoding device
400
. The turbo decoding device
400
has a plurality of soft output decoding circuits
401
-
1
through
401
-m corresponding to the number of the coded data (received data) outputted from the turbo coding device
300
. The soft output decoding circuits
401
-
1
through
401
-m are constructed respectively by using a so-called soft output decoding system such as a MAP (Maximum A posteriori Probability) decoder and a SOVA (Soft Output Viterbi Algorithm) decoder or the like, having the function of calculating the probability that input data on the coding side will take 0 or 1.
The operation of the turbo decoding device
400
shown in
FIG. 21
will be described. Received data (coded data) D
401
-
1
through D
401
-m are respectively supplied to the soft output decoding circuits
401
-
1
through
401
-m. The respective decoding circuits
401
-
1
through
401
-m respectively perform a repetitive decoding operation several times or several tens of times, utilizing estimated probability-value data with respect to the input data excluding termination bits on the coding sides with one another. The final decoded data D
402
are outputted from an arbitrary decoding circuit (corresponding to the decoding circuit
401
-
1
in FIG.
21
).
FIG. 22
shows the relationship between the numbers of bits for the received data D
401
-
1
through D
401
-m, estimated probability-value data and decoded data D
402
employed in the turbo decoding device
400
and corresponds to the relationship between the respective numbers of bits employed in the turbo coding device
300
shown in FIG.
15
. The soft output decoding circuits
401
-
1
through
401
-m respectively calculate k-bit estimated probability-value data with respect to the input data excluding the termination bits from the (n
1
+t
1
) through n
m
+t
m
)-bit received data D
401
-
1
through D
401
-m. Thereafter, the k-bit estimated probability-value data are transferred between the respective decoding circuits, so that the k-bit decoded data D
402
are finally outputted.
Meanwhile, in the aforementioned turbo coding device
300
, the interleavers
302
-
1
through
302
-(m−1) n

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