Tuning programmable logic devices for low-power design...

Details Tuning programmable logic devices for low-power design... Tuning programmable logic devices for low-power design...

2004-02-20

2009-06-16

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07549139

ABSTRACT:
A method of operating a programmable logic device includes the steps of using a full VDDsupply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDDsupply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDDsupply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

REFERENCES:
patent: 4962341 (1990-10-01), Schoeff
patent: 5303390 (1994-04-01), Little
patent: 5362989 (1994-11-01), Hennedy
patent: 5519663 (1996-05-01), Harper et al.
patent: 5568062 (1996-10-01), Kaplinsky
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5612892 (1997-03-01), Almulla
patent: 5615162 (1997-03-01), Houston
patent: 5671149 (1997-09-01), Brown
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5712790 (1998-01-01), Ditlow et al.
patent: 5801548 (1998-09-01), Lee et al.
patent: 5811962 (1998-09-01), Ceccherelli et al.
patent: 5825662 (1998-10-01), Trimberger
patent: 5832286 (1998-11-01), Yoshida
patent: 5914873 (1999-06-01), Blish, II
patent: 5946257 (1999-08-01), Keeth
patent: 5958026 (1999-09-01), Goetting et al.
patent: 6038386 (2000-03-01), Jain
patent: 6114843 (2000-09-01), Olah
patent: 6148390 (2000-11-01), MacArthur
patent: 6160418 (2000-12-01), Burnham
patent: 6169419 (2001-01-01), De et al.
patent: 6172518 (2001-01-01), Jenkins, IV et al.
patent: 6208171 (2001-03-01), Kumagai et al.
patent: 6384626 (2002-05-01), Tsai et al.
patent: 6466049 (2002-10-01), Diba et al.
patent: 6489804 (2002-12-01), Burr
patent: 6583645 (2003-06-01), Bennett et al.
patent: 6631502 (2003-10-01), Buffet et al.
patent: 6710621 (2004-03-01), Devlin et al.
patent: 6711719 (2004-03-01), Cohn et al.
patent: 6747478 (2004-06-01), Madurawe
patent: 6839888 (2005-01-01), Gupta
patent: 6885563 (2005-04-01), Panella et al.
patent: 6936917 (2005-08-01), Lopata et al.
patent: 6950998 (2005-09-01), Tuan
patent: 6960934 (2005-11-01), New
patent: 6968467 (2005-11-01), Inoue et al.
patent: 7003620 (2006-02-01), Avraham et al.
patent: 7078932 (2006-07-01), Swami
patent: 7080341 (2006-07-01), Eisenstadt et al.
patent: 7098689 (2006-08-01), Tuan et al.
patent: 7109748 (2006-09-01), Liu et al.
patent: 7112997 (2006-09-01), Liang et al.
patent: 7135886 (2006-11-01), Schlacter
patent: 7170315 (2007-01-01), Bakker et al.
patent: 7313708 (2007-12-01), Oshins
patent: 2003/0030326 (2003-02-01), Shenai et al.
patent: 2003/0218478 (2003-11-01), Sani et al.
patent: 2004/0145955 (2004-07-01), Mizuno et al.
patent: 2005/0091547 (2005-04-01), Hanrieder et al.
patent: 2005/0201174 (2005-09-01), Klein
patent: 2006/0053246 (2006-03-01), Lee
patent: 2006/0069851 (2006-03-01), Chung et al.
patent: 2006/0202713 (2006-09-01), Sergey Shumarayev
patent: 2007/0001720 (2007-01-01), Li et al.
patent: 2007/0164785 (2007-07-01), He
US 6,981,160, 12/2005, Thaker et al. (withdrawn)
U.S. Appl. No. 10/606,619, filed Jun. 26, 2003, New et al.
U.S. Appl. No. 10/377,857, filed Feb. 28, 2003, Blodget et al.
He, Lei; “Power Efficient FPGA: Circuit, Fabrics and CAD Algorithms,” Presentation on Feb. 13, 2004, 50 pages, at Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124, available from EE Department, UCLA, at http://eda.ee.ucla.edu/.
FPGA 2004 Advance Program; ACM/SIGDA Eleventh international Symposium of Field Programmable Gate Arrays, Feb. 22-24, 2004, 6 pages, at Monterey Beach Hotel, Monterey, California, available at http://fpga20044.ece.ubc.ca/.
Takahashi, M. et al.; “A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme,” Nov. 1998, pp. 1772-1780, vol. 33, No. 11, available from IEEE Journal of Solid-State Circuits, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
U.S. Appl. No. 10/783,589, filed Feb. 20, 2004, Look et al.
Mutoh, S. et al., “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” Aug. 1995, pp. 847-854, vol. 30, No. 8, available from IEEE Journal of Solid-State Circuits, 3, Park Avenue, 17th Floor, New York, NY 10016-5997.
Kuroda, T., et al., A 0.9V, 150-MHz, 1-mW, 4 mm22-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme, 1996, pp. 1770-1779, vol. 31, No. 11, available from IEEE Journal of Solid-State Circuits, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Inukai, T. et al., “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration,” 2000, pp. 409-412, available from IEEE Journal of Solid-State Circuits, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Hamzaoglu, F. et al., “Circuit-Level Techniques to Control Gate Leakage for sub-100nm CMOS,” ISLPED, Aug. 12-14, 2002, pp. 60-63, available from IEEE Journal of Solid-State Circuits, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Jae Y. Park, Mark G. Allen; “A Comparison of Micromachined Inductors with Different Magnetic Core Materials”; 1996 Electronic Components and Technology Conference; 1996 IEEE; pp. 375-381.
Thomas D. Burd et al.; “A Dynamic Voltage Scaled Microprocessor System”; 2000 IEEE; IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000; pp. 1571-1580.
Anthony J. Stratakos et al.; “A Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System”; 1994 IEEE; pp. 619-626.
Anthony John Stratakos; “High-Efficiency Low-Voltage DC-DC Conversion for Portable Applications,” Chapter 3; “DC-DC Converter Fundamentals”; pp. 42-78.
Allen/Holberg; Chapter 10; “Bandgap Voltage Reference”; Apr. 12, 2000; downloaded on Jan. 3, 2006 from www.ece.utexas.edu/˜holberg/lecture—notes/bandgap.pdf; pp.1-5.
Microchip Technology Inc.; “Micropower Voltage Supervisors”; MCP102/103/121/131; Copyright 2005; downloaded on Jan. 3, 2006 from ww1.microchip.com/downloads/en/DeviceDoc/21906b.pdf; pp. 1-28.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Oct. 14, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 19-71.
Xilinx, Inc., “Spartan-3L Low Power FPGA Family”, Preliminary Product Specification, DS313, Sep. 15, 2005, v1.1, pp. 1-10, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.-3L.
Intel Corporation, “Intel PXA27 Processor Family Power Requirements”, Application Note, 2004, pp. 1-36, available from Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119.
Nowka, Kevin J., A32-bit PowerPC System-on-a-Chip With Support For Dynamic Voltage Scaling and Dynamic Frequency Scaling, Nov. 2002, pp. 1441-1447, vol. 37, No. 11, IEEE Journal of Solid-State Circuits, Available from IEEE; 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Texas Instruments (Benchmarq) - Datasheet BQ4011 (32x8 nonvolatile SRAM) Aug. 1993 pp. 1-11.
Texas Instruments - Datasheet BQ4011 (32x8 nonvolatile SRAM) May 1999 pp. 1-15.
U.S. Appl. No. 10/971,934 filed Oct. 22, 2004, Jenkins, Jesse H. IV, entitled “ Low Power Zones For Programmable Logic Devices”, Xilinx, Inc., San Jose, CA.
U.S. Appl. No. 11/268,265 filed Nov. 4, 2005, Rahman, Arifur, et al. entitled “ Implementation of Low Power Standby Modes For Intergrated Circuits”, Xilinx, Inc., San Jose, CA.
U.S. Appl. No. 11/325,888 filed Jan. 4, 2006, Tuan, Tim, entitled “Programmable Low Power Modes For Embedded Memory Blocks”, Xilinx Inc., San Jose, CA.
U.S. Appl. No. 11/326,542 filed Jan. 4, 2006, Jacobson, Neil G.. et al., entitled &

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