Tungsten silicide deposition process

Details Tungsten silicide deposition process Tungsten silicide deposition process

1997-01-13

2002-01-01

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C438S657000, C438S680000

Reexamination Certificate

active

06335280

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microelectronic device fabrication, and more particularly, to a method of forming tungsten or tungsten silicide layers for use in gate metallizations and local interconnects in a semiconductor integrated circuit.
2. Description of the Related Technology
In microelectronic devices common in the art, a field effect transistor
10
is formed in a semiconductor
11
by interposing a gate
12
of the transistor between heavily doped regions comprising the source
14
and drain
16
of the transistor as shown in FIG.
1
. In older semiconductor devices, the gate
12
comprised doped polycrystalline silicon (poly) over the gate dielectric
20
. However, as the dimensions of transistors and their interconnections have decreased into the submicron region, the high resistivity of doped poly adversely impacts the switching speed of field effect transistors
10
. Thus, to increase the switching speed of a transistor
10
, semiconductor manufacturers use a multilayer structure
18
including a metallic layer, such as tungsten (W) or tungsten silicide (WSi
2
), to reduce the resistivity of gates
12
and local interconnect lines so as to increase the operating speed of circuits formed from interconnected transistors. Thus, the gate
12
of a current transistor
10
typically comprises a multilayer structure
18
on top of a thin silicon oxide layer
20
in contact with the silicon semiconductor
11
. The multilayer structure
18
comprises a doped poly layer
22
in contact with the silicon oxide layer
20
and a metallic layer
24
comprising W or WSi
2
in contact with the poly layer
22
.
During the formation of the microelectronic device, a metallic W or WSi
2
layer may be deposited either selectively or nonselectively. In U.S. Pat. No. 4,913,929, Moslehi, et al., disclose several selective and nonselective methods for depositing a W layer using a cold wall single wafer thermal/microwave remote plasma multiprocessing reactor. Moreover, as described by Leusink, et al., in
J. Appl. Phys.
72, 490 (1992), selective deposition of W or WSi
2
proceeds by the following well known chemical reactions:
2WF
6
(g)+3Si(s)→2W(s)+3SiF
4
(g)  (1)
WF
6
(g)+3Si(s)→W(s)+3SiF
2
(g)  (2)
W(s)+2Si(s)→WSi
2
  (3)
2WF
6
(g)+7Si(s)→2WSi
2
(s)+3SiF
4
(g)  (4)
Reactions 1 and 2 describe the formation of tungsten. After the tungsten has been formed by either reaction 1 or 2, it can react further with the underlying Si to form WSi
2
(reaction 3). Reaction 4 describes the direct formation of WSi
2
. Thus, the basic reaction is the silicon (Si) reduction of tungsten hexafluoride (WF
6
) gas, a displacement reaction where exposed Si is converted to a solid layer of W thereby releasing the displaced Si in the volatile gases SiF
2
and SiF
4
. In contrast to nonselective or blanket depositions, these reactions cause selective deposition of W because only those Si regions exposed to WF
6
on the semiconductor
11
react to form a deposited W layer. There is no conversion to W of regions of the semiconductor
11
having exposed regions comprising materials other than Si, such as silicon oxide (SiO
2
) or silicon nitride (Si
3
N
4
).
According to reactions (1) and (2), every nanometer of W formed consumes approximately two nanometers of the exposed Si. Thus, as noted by Leusink, et al., the Si reduction of WF
6
should be suppressed as the etching of exposed Si, such as source or drain regions, is an undesired result. To prevent or reduce undesired etching of exposed Si regions, combinations of WF
6
gas and reducing agents, such as the gases H
2
, SiH
4
or GeH
4
, have been used for the chemical vapor deposition (CVD) of W. Currently, tungsten CVD by WF
6
/H
2
or WF
6
/SiH
4
are the preferred methods used in the microelectronics industry. However, in
IEEE Trans. Electron Devices
, 37, 577 (1990), Kobayashi, et al., describe applying the selective deposition of W to form a W contact (plug) by substitution of undoped poly by W.
FIG. 2
a
illustrates a cross sectional view of a semiconductor wafer prepared for the substitution of undoped poly by W. An oxide layer
32
resides on the silicon substrate
30
. A barrier layer
34
comprising titanium nitride (TiN) resides on the silicon oxide layer
32
and within the contact aperture
38
, where the TiN barrier layer
34
contacts the silicon substrate
30
. Lastly, a conformal poly layer
36
is deposited over the TiN barrier layer
34
.
Referring now to
FIG. 2
b
, an etch back of the poly layer
36
is performed to remove poly from the TiN barrier layer
34
. Note that the etch back step slightly over etches the poly layer
34
so that the remaining poly
36
is slightly recessed within the aperture
38
. Referring now to
FIG. 2
c
, a thin chemical oxide layer
40
is formed over the poly
36
within the aperture
38
. This chemical oxide layer
40
enhances the subsequent selective deposition of W. Lastly, substitution of poly
36
by W using WF
6
gas occurs to form a W plug
42
as shown in
FIG. 2
d
. Note that the entire volume of poly
36
(
FIG. 2
c
) within the contact aperture
38
is replaced by W so as to form a W plug
42
. The TiN barrier layer
34
serves to stop the substitution of Si by W during the selective deposition of a contact. Moreover, this technique is also well adapted to via fills in multilevel metal layer interconnections. However, the TiN barrier layer
34
is not needed in a via fill process as the lower level metal serves to stop the Si substitution by W. Thus, selective deposition of W techniques have found only limited application in contact formation and via fill because of the desire to avoid consumption of exposed Si regions in other device fabrication applications.
Although Moslehi, et al., disclose in U.S. Pat. No. 4,913,929 that several wafer processing steps can be done sequentially in a single reactor, semiconductor manufacturers currently use multiple reactors of significantly different configuration to form and interconnect the many layers needed in a microelectronic device. For example, a manufacturer may use a cluster tool, such as an Applied Materials Centura, having a reactor chamber dedicated to the deposition of poly and also having a reactor chamber of significantly different configuration dedicated to the deposition of WSi
2
. The present art for tungsten silicide formation uses a gas mixture consisting of tungsten hexafluoride and silane or dichlorosilane. The tungsten silicide deposits according to the following reactions:
2WF
6
+7SiH
4
→2WSi
2
+2SiF
4
+14H
2
  (5)
2WF
6
+10SiH
2
Cl
2
→2WSi
2
+3SiF
4
+3SiCl
4
+8HCl+6H
2
  (6)
The nonselective WSi
2
deposition results in deposition of WSi
2
on the reactor walls and other areas exposed to the WF
6
and SiH
4
gas. Thus, this WSi
2
reactor chamber requires downtime for frequent etching (cleaning) to remove the WSi
2
buildup on exposed areas.
The use of multiple different reactors often results from a strategy to prevent incompatible chemical reactions and materials produced during the formation of a prior layer from impacting the formation of a current or subsequent layer in the same reactor. This strategy is of critical importance to a semiconductor manufacturer as minuscule amounts of impurities in any single layer of a microelectronic device often result in device failures and scrap. At the same time, however, the need for multiple reactors of different configuration creates substantial operational issues in addition to the significant capital funds required to procure multiple different reactors. For example, the manufacturer has to maintain spares for each of the multiple reactor configurations used in its factory at a considerable cost for spares inventory, warehousing and personnel to manage spares.
To improve their operations, microelectronic device manufacturers require fabrication methods and systems tha

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