Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-19
2001-04-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S668000, C438S680000, C438S685000
Reexamination Certificate
active
06218298
ABSTRACT:
FIELD OF INVENTION
This relates to the filling of relatively deep vertical trenches, and more particularly, to such trenches for use in dynamic random access memories as the storage capacitors providing the storage node.
BACKGROUND OF THE INVENTION
There is interest in the use of trench capacitors for use as the storage node in the memory cells of dynamic random access memories (DRAMs). Such capacitors offer the potential of relatively large capacitances with the consumption of relatively little surface area, which permits a higher density of memory cells in a silicon chip of a given size. Typically such vertical cells have been filled with doped polysilicon because of its convenience of use.
However, as the cross section of the vertical trench has been shrunk while its depth has been increased to get a desired capacitance with smaller consumption of chip surface area, the resulting increased resistance has become a matter of concern, since it increases the time to charge/discharge the capacitor, thereby limiting performance. While it has been recognized that the substitution of a material, such as a metal, for the doped polysilicon fill, would result in a lower resistance, it has proven difficult to find a suitable metal for filling trenches with aspect ratios much in excess of 10. The present invention is addressed to this problem.
SUMMARY OF THE INVENTION
The present invention is directed to a process for filling with tungsten a vertical trench with an aspect ratio of at least twenty in a silicon substrate that comprises heating the silicon chip in a chamber for chemical vapor deposition to a temperature of about 375° C. or less while flowing into the chamber a tungsten compound suitable for chemical vapor deposition. In a preferred embodiment for achieving aspect ratios in the range of 30 to 40, the tungsten compound is WF
6
, the temperature is between 350° C. and 375° C. and before the deposit of the tungsten, there is formed over the walls of the trench a nucleation film by flowing through the chamber a mixture of SiH
4
, H
2
and WF
6
.
REFERENCES:
patent: 5202754 (1993-04-01), Bertin et al.
patent: 5795824 (1998-08-01), Hancock
patent: 6022800 (2000-02-01), Ho et al.
patent: 6066366 (2000-05-01), Berenbaum et al.
Pierson, H.O., Handbook of Chemical Vapor Deposition (CVD): Principles, Technology and Applications. Noyes Publications, 1992. pp. 148-151.*
Tanaka et al., “Integration of CVD W on IMP Ti and TiN”; Proceedings on 5th International Conference on Solid-State and Integrated Circuit Technology, 1998. pp. 207-210.
Chaudhuri Olik
Infineon Technologies North America Corp.
Peralta Ginette
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