Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-24
2002-10-15
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S381000, C438S447000, C438S241000
Reexamination Certificate
active
06465308
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to the structure and manufacturing process of a FET semiconductor device for ESD protection of electronic circuit devices and more particularly to a tunable threshold voltage thick field oxide device with improved ESD circuit protection characteristics for higher voltage applications
(2) Description of Prior Art
Because of high input impedance and thin oxide gate structures, the problem of electrostatic discharge damage (ESD) with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pads usually have a protective device connected between the I/O pad and the internal circuits as shown in
FIG. 1A
, which allows the ESD current to be shunted to ground. In the prior art, for circuit applications in the range of 5 volts, an active device thin oxide gate field effect transistor is often used as shown in FIG.
1
A. With the prior art method, the FET source and gate are tied to ground and the drain is connected to the input/output terminal which serves as the I/O to the internal logic circuits
20
. It is important to note that in his prior art configuration, the FET gate is tied to a second voltage source, typically ground. Also depicted in
FIG. 1A
is a parasitic npn bipolar transistor
14
, formed from the parasitic elements of the FET source and drain and the substrate.
The protection mechanism is initiated by a threshold trigger voltage as shown in
FIG. 1B
whereby the ESD current is shunted primarily through the parasitic bipolar by a breakdown characteristic. For logic voltage applications of 5 volts, this trigger voltage level is typically in the 10 to 15 volt range which is generally adequate to protect the internal logic circuits from damage. After current flow initiated by Vt, there results a snapback characteristic to Vsp. The region from Vsp to Vtt is known as the clamping region whereby the ESD current is shunted to ground. Beyond Vtt damage to the protection device structure can occur
Another important characteristic of the ESD protection device is that it must not interfere with the operation of the devices it is designed to protect, while at the same time providing good protection when abnormal or ESD voltage incidents occur. However, in the 9 volt to 16 volt application range, sometimes referred to as high voltage application range, the design and processing of the active thin gate FET device to enable it to be compatible with the higher voltage can result in a trigger voltage point of 22 volts or greater, that is often higher than desired for the application. It is also highly desirable to be able to control or set the initiation or trigger point of the ESD protection device to match the application requirements as closely as possible. The invention provides a novel and unique structure that provides a degree of control of the trigger point for the protection device used for the higher voltage applications.
U.S. Pat. No. 4,760,433 issued to Young et al., describes an electrostatic discharge (ESD) protection circuit including complementary bipolar transistors having collectors connected to an input and base and emitters connected together to a respective voltage source. The bipolar transistors are lateral transistors having a field plate over the base region and spaced laterally from the laterally spaced collector and emitter regions. The base may include increased impurity surface regions extending from the emitter and collector to the gate to increase the beta and decrease the collector base breakdown.
U.S. Pat. No. 5,707,886 to Consiglio et al., illustrates an integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from ESD events.
U.S. Pat. No. 5,869,366 issued to Honnigford et al., teaches an IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes a metal gate field oxide device having an n-type source region, an n-type drain region, and a p-type field implant diffusion between the source and drain regions. Overlapping their masks form s the field implant diffusion and drain/collector regions, such that a lower breakdown voltage is achieved between the NPN collector and the substrate and field implant (the NPN base).
U.S. Pat. No. 5,894,153 issued to Walker et al., describes an integrated circuit protected by an SCR that conducts electrostatic discharge pulses from the pad directly to a current sink. The SCR includes a subregion underneath a field oxide that has a field implant that increases the dopant concentration. The field implant lowers the SCR trigger voltage, so that the SCR triggers before an ESD pulse can cause latch-up or damage in other devices in the integrated circuit.
The following technical reports also refer to the subject of ESD protection in MOS circuits.
“Design Methodology for Optimizing Gate driven ESD Protection Circuits in Submicron CMOS Processes”, by Chen et al., EOS/ESD Symposium, 1997 Proceedings Pages 230-239.
“The Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors”, by Chen et al., IEEE Transactions Electron Devices vol. 35, no. 12, pp. 2140-2150.
SUMMARY OF THE INVENTION
Accordingly, it is the primary objective of the invention to provide an effective and manufacturable method and structure for improving high voltage application semiconductor device resistance to the potential damage caused by the phenomenon known as electrostatic discharge (ESD) by utilizing a thick field oxide field effect transistor (FET) connected to an input/output pad of an integrated circuit device.
It is a further objective of the invention to improve ESD protection by providing a tunable or adjustable threshold voltage (Vt) of the thick field oxide FET device by using an N-field implant during device processing.
Another objective of the invention is to provide a capability to reduce the threshold of the thick field oxide FET ESD protection device, and hence improving ESD protection, without unduly reducing the thickness of the thick field oxide which essentially forms the gate oxide for the FET protection device
A still additional objective of the invention is to provide the improved ESD protection without changing the characteristics of the internal circuits being protected and by using a process compatible with the process of integrated MOS device manufacturing.
The above objectives are achieved in accordance with the methods of the invention which describes a structure and a process for manufacturing semiconductor devices with improved ESD protection. A thick gate oxide field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input to the internal circuits to achieve this ESD protection. Thick field oxide regions similar to those used for FET device isolation areas are formed on a semiconductor substrate and appropriate dopants are used to form source/drain regions in proximity to and on either side of the thick field oxide gate element essentially forming a thick oxide N channel metal oxide semiconductor field effect transistor (NMOSFET) with an associated parasitic npn bipolar transistor. A field implant is used to provide a dopant region under the thick oxide gate element. This has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal chip active semiconductor circuits. The thick oxide field protection device is particularly beneficial for voltage applications of 9 volts and above. The gate and drain of the thick oxide FET device and the collector of the parasitic npn bipolar transistor are connected to the input connection pad of the internal semiconductor circuits. This configuration enhances sensitivity to ESD events. The FET source and the emitter and base of the parasitic bipolar transistor are connected to a second voltage source, typically ground, providing a pa
Cheng Tao
Wu Lin-June
You Jyh-Cheng
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tsai Jey
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