Tunable stressed polycrystalline silicon on dielectrics in...

Details Tunable stressed polycrystalline silicon on dielectrics in... Tunable stressed polycrystalline silicon on dielectrics in...

2011-01-04

2011-01-04

Nguyen, Cuong Q (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S301000, C257S310000, C438S243000, C438S244000, C438S245000, C438S246000, C438S247000, C438S386000, C438S387000, C438S388000, C438S389000, C438S390000

Reexamination Certificate

active

07863130

ABSTRACT:
System and method for creating stressed polycrystalline silicon in an integrated circuit. A preferred embodiment includes manufacturing an integrated circuit, including forming a trench in an integrated circuit substrate, forming a cavity within the integrated circuit substrate, wherein the cavity is linked to the trench, depositing a dielectric layer within the cavity, and depositing polycrystalline silicon over the dielectric layer, wherein an inherent stress is induced in the polycrystalline silicon that grows on the dielectric layer. The dielectric layer may be, for example, silicon aluminum oxynitride (SiAlON), mullite (3Al2O3.2SiO2), and alumina (Al2O3).

REFERENCES:
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Van Zutphen, A.J.M.M., et al., “Structure of thin polycrystalline silicon films on ceramic substrates,” Journal of Crystal Growth 223, 2001, N.H. Elsevier, pp. 332-340.

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