Tunable sidewall spacer process for CMOS integrated circuits

Details Tunable sidewall spacer process for CMOS integrated circuits Tunable sidewall spacer process for CMOS integrated circuits

2005-06-21

2005-06-21

Lee, Hsien Ming (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S216000, C438S230000, C438S232000

Reexamination Certificate

active

06908800

ABSTRACT:
A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack (30) is formed over the silicon substrate (10). Ion implantation is performed of a first species and a second species to produce the doping profiles (70, 80, 90, 100) in the input-output transistors.

REFERENCES:
patent: 5254866 (1993-10-01), Ogoh
patent: 5963803 (1999-10-01), Dawson et al.
patent: 5994743 (1999-11-01), Masuoka
patent: 6020231 (2000-02-01), Wang et al.

Affiliated with

Also associated with

Rating

Tunable sidewall spacer process for CMOS integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tunable sidewall spacer process for CMOS integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tunable sidewall spacer process for CMOS integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3508670