TTL input buffer with on-chip reference bias regulator and decou

Details TTL input buffer with on-chip reference bias regulator and decou TTL input buffer with on-chip reference bias regulator and decou

1994-08-23

1996-05-14

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 71, 327541, H03K 1716

Patent

active

055171311

ABSTRACT:
An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.

REFERENCES:
patent: 4656373 (1987-04-01), Pons
patent: 4874967 (1989-10-01), Deane
patent: 4876465 (1989-10-01), Podkowa
patent: 4988897 (1991-01-01), Jeong
patent: 5057715 (1991-10-01), Larsen
patent: 5214320 (1993-05-01), Truong
patent: 5376843 (1994-12-01), Tien

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