Triple redundant latch design with low delay time

Details Triple redundant latch design with low delay time Triple redundant latch design with low delay time

2007-05-08

2007-05-08

Barnie, Rexford (Department: 2819)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C326S010000, C327S197000, C327S199000, C365S154000, C365S200000, C714S797000

Reexamination Certificate

active

10825398

ABSTRACT:
In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.

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