Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-07
2003-12-30
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S765000, C438S787000
Reexamination Certificate
active
06670248
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of semiconductor devices within integrated circuits and, more specifically, to circuits requiring the formation of gate oxide layers having varying degrees of thickness and composition.
2. Description of the Related Art
The fabrication of integrated circuits often requires the formation of dielectric layers, such as gate oxide layers, with varying degrees of thickness and composition. The necessity of varying thicknesses is typically the case when the circuit contains semiconductor devices operating at different voltages. For example, high voltage power transistors and transistors used to program EEPROM devices require thicker gate oxides than lower voltage transistors used in memory storage in DRAM circuits. Furthermore, as device size continues to decrease, the ultra-thin gate oxides required to eliminate problems such as short-channel effects in MOSFETs are also preferably formed of dielectric materials having high dielectric constants (high-k dielectrics). Thus, not only must the fabrication process enable the formation of dielectrics with varying thicknesses, it must also allow the formation of dielectrics with different compositions. Clearly, such a process should also be efficient and produce dielectric layers with integrity and quality.
Hattangady et al. (U.S. Pat. No. 5,970,345) teach a method for forming an oxide layer of two different thicknesses for an integrated circuit having both high and low voltage MOS transistors. The method involves the formation of a first oxide layer. A sacrificial layer is formed over the first oxide layer and partially removed to allow selective etching away of the first oxide layer. A second oxide layer is then formed over the oxide-free region and over the sacrificial layer covered first oxide region, whereby the sacrificial layer is consumed by the second oxide and the remaining first oxide and second oxide over it together form a layer of double thickness.
Chwa et al. (U.S. Pat. No. 6,147,008) teach a method for forming a gate oxide with three different thicknesses. A first layer is deposited to the desired maximum thickness. The portion of the layer that is to remain is covered by a photoresist. A nitrogen implant is driven into a small area of the substrate through the uncovered portion of the first oxide layer. The purpose of the implant is to locally modify the crystal structure of the substrate and alter the thickness of a second oxide layer. The uncovered first layer is then removed from the substrate and a second, thinner layer is grown. The second layer has a thinner portion over the nitrogen-implanted region.
Song (U.S. Pat. No. 6,191,049 B1) also teach a method of forming a gate oxide with varying thicknesses by the use of ion implantation into the substrate to modify the oxide growth properties of the substrate over the implanted regions. The method teaches the use of two different ion species, nitrogen and fluorine, implanted to different depths and concentrations, by which method different subsequent oxide growth thicknesses are achieved.
Zhong et al. (U.S. Pat. No. 6,268,251 B1) teach a method for fabricating multiple thickness gate oxide layers. In accord with the method, a first layer of gate oxide is deposited to a first thickness, which is the thickest of the oxide layers. A layer of polysilicon is deposited over the first gate oxide layer and planarized. The polysilicon layer is masked to define a region where a second oxide thickness is required, and the polysilicon and the oxide layer beneath it are etched away from the substrate surface. A second oxide layer is now grown, to a second thickness, which is the intermediate thickness, on the exposed surface of the substrate. A second polysilicon layer is now deposited on the second oxide layer and planarized. As before, the polysilicon is masked to define a region where a third oxide thickness, which is the thinnest, is required. The previous steps are now repeated.
As device sizes become increasingly small, the use of selective ion implantations to control gate oxide growth, as taught in the prior art cited above, will become impractical. In addition, it is desirable to form the varying thickness layers in as cost efficient a manner as possible, which requires the minimization of fabrication steps. The present invention accomplishes its objects without ion implantations and with a smaller number and simpler process steps than those of the prior art.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a simple and efficient method for forming dielectric layers of varying thicknesses on a semiconductor substrate.
A second object of this invention is to provide a simple and efficient method for forming dielectric layers of varying compositions on a semiconductor substrate.
A third object of this invention is to provide a simple and efficient method for forming dielectric layers of varying compositions on a semiconductor substrate, wherein the thinnest layer is a single layer of high-k dielectric material and the layers of intermediate and greatest thickness are double layers comprising a layer of high-k dielectric material formed over a layer of silicon oxide.
A fourth object of the present invention is to provide a simple and efficient method for forming MOS/CMOS devices requiring varying thicknesses and compositions of their gate oxide layers.
In accord with the objects of this invention there is provided a simple and efficient method for forming a dielectric layer of varying thickness and composition on a semiconductor substrate comprising the steps of: 1) forming a first dielectric layer over a semiconductor substrate; 2) removing a first portion of that layer to expose the semiconductor substrate surface thereunder; 3) forming a second, thinner dielectric layer over the substrate surface exposed thereby; 4) removing a second portion of the first dielectric layer to expose the semiconductor substrate surface thereunder; 5) forming a third, blanket, dielectric layer over the second dielectric layer, the remaining portion of the first dielectric layer and the exposed semiconductor substrate. In the preferred embodiment of this invention, the first and second dielectric layers are layers of silicon oxide (SiO
2
) and the third, blanket layer, is a layer of high-k dielectric. It is further noted that a layer of gate electrode material, such as doped polysilicon, can be deposited over the third dielectric layer and patterned to form gate dielectrics for MOS or CMOS devices.
REFERENCES:
patent: 5576573 (1996-11-01), Su et al.
patent: 5970345 (1999-10-01), Hattangady et al.
patent: 6147008 (2000-11-01), Chwa et al.
patent: 6191049 (2001-02-01), Song
patent: 6268251 (2001-07-01), Zhong et al.
patent: 6352876 (2002-03-01), Bordogna et al.
patent: 2002/0027681 (2002-03-01), Aitken
Ang Chew Hoe
Lin Wenhe
Zheng Jia Zhen
Chartered Semiconductor Manufacturing Ltd.
Everhart Caridad
Pike Rosemary L. S.
Saile George O.
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