Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-10-06
2011-12-27
Nguyen, Dao H (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
08084825
ABSTRACT:
A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.
REFERENCES:
patent: 6110837 (2000-08-01), Linliu et al.
patent: 6358791 (2002-03-01), Hsu et al.
patent: 6387739 (2002-05-01), Smith, III
patent: 6605514 (2003-08-01), Tabery et al.
patent: 6664173 (2003-12-01), Doyle et al.
patent: 6787439 (2004-09-01), Ahmed et al.
patent: 6794279 (2004-09-01), Stephen et al.
patent: 7301206 (2007-11-01), Yeo et al.
patent: 2006/0094230 (2006-05-01), Fuller et al.
patent: 2007/0045230 (2007-03-01), Keller et al.
patent: 2009/0101985 (2009-04-01), Fuller et al.
Dalton Timothy J.
Fuller Nicholas C.
Zhang Ying
International Business Machines - Corporation
Nguyen Dao H
Nguyen Tram H
Percello, Esq. Louis J.
Scully , Scott, Murphy & Presser, P.C.
LandOfFree
Trilayer resist scheme for gate etching applications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Trilayer resist scheme for gate etching applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trilayer resist scheme for gate etching applications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4305884