Tri-gate field-effect transistors formed by aspect ratio...

Details Tri-gate field-effect transistors formed by aspect ratio... Tri-gate field-effect transistors formed by aspect ratio...

2011-07-12

2011-07-12

Garber, Charles D (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

With lattice constant mismatch

C257SE33050, C257SE29246, C257SE29296, C257SE29298, C257SE21092, C257SE21097, C257SE21102, C257SE21133, C257SE21403, C257SE21562, C438S044000, C438S283000, C438S481000

Reexamination Certificate

active

07977706

ABSTRACT:
Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

REFERENCES:
patent: 2002/0084000 (2002-07-01), Fitzgerald
patent: 2005/0073028 (2005-04-01), Grant et al.
patent: 2005/0250285 (2005-11-01), Yoon et al.
patent: 02062090 (1990-03-01), None

Affiliated with

Also associated with

Rating

Tri-gate field-effect transistors formed by aspect ratio... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tri-gate field-effect transistors formed by aspect ratio..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tri-gate field-effect transistors formed by aspect ratio... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2722105