Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-04-08
2008-04-08
Gurley, Lynne (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S157000, C438S176000, C438S142000, C438S149000, C438S197000, C257S330000, C257SE21442
Reexamination Certificate
active
07354832
ABSTRACT:
A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
REFERENCES:
patent: 2004/0113171 (2004-06-01), Chiu et al.
patent: 2005/0156171 (2005-07-01), Brask et al.
patent: 2005/0158970 (2005-07-01), Chau et al.
patent: 2006/0091428 (2006-05-01), Yeo et al.
Liu et al. “Advanced FinFET technology: TiN metal-gate CMOS and 3T/4T device integration”, 2005 IEEE International SOI Conference, Proceedings, Oct. 3-6, 2005, pp. 219-220.
U.S. Appl. No. 10/227,068; Title: Tri-Gate Devices and Methods of Fabrication; Inventor: Chau et al.; Filing Date: Aug. 23, 2002.
U.S. Appl. No. 10/750,061; Title: Nonplanar Transistors with Metal Gate Electrodes; Inventor: Brask et al.; Filing Date: Dec. 30, 2003.
Doyle Brian S.
Kavalieros Jack T.
Rachmady Willy
Shah Uday
Gurley Lynne
Hsieh Hsin-Yi (Steven)
Intel Corporation
Ortiz Kathy
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