Trenches to reduce lateral silicide growth in integrated...

Details Trenches to reduce lateral silicide growth in integrated... Trenches to reduce lateral silicide growth in integrated...

2006-04-04

2006-04-04

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S213000, C257S288000, C257S368000, C257S386000, C257S387000, C257S388000, C438S584000, C438S597000, C438S682000, C438S683000

Reexamination Certificate

active

07023059

ABSTRACT:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

REFERENCES:
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patent: 5648175 (1997-07-01), Russell et al.
patent: 5665990 (1997-09-01), Kang et al.
patent: 5918141 (1999-06-01), Merrill
patent: 6333255 (2001-12-01), Sekiguchi
patent: 6518155 (2003-02-01), Chau et al.
patent: 6580143 (2003-06-01), Yoshida et al.
patent: 6770942 (2004-08-01), Iinuma

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