Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-04
2001-10-16
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S268000, C438S269000, C438S270000
Reexamination Certificate
active
06303437
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and methods of manufacture, and more particularly, to semiconductor devices and methods of manufacture including a trenched gate.
BACKGROUND OF THE INVENTION
Conventional semiconductor non-volatile memories, such as read-only memories (ROMs), erasable-programmable ROMs (EPROMs), electrically erasable-programmable ROMs (EEPROMs), and flash EEPROMs are typically constructed using a double-poly structure. Referring now to
FIG. 1
, there is shown a cross-sectional view of the device structure of a conventional nonvolatile memory device
100
including a substrate
102
of a semiconductor crystal such as silicon. The device
100
also includes a channel region
104
, a source region
106
, a drain region
108
, a floating gate dielectric laser
110
, a floating gate electrode
112
, an inter-gate dielectric layer
114
, and a control gate electrode
116
. The floating gate dielectric layer
110
isolates the floating gate electrode
112
from the underlying substrate
102
while the inter-gate dielectric layer
114
isolates the control gate electrode
116
from the floating gate electrode
112
. As shown in
FIG. 1
, the floating gate dielectric layer
110
, the floating gate electrode
112
, the inter-gate dielectric layer
114
, and the control gate electrode
116
are all disposed above the surface of substrate
102
. The device structure of conventional non-volatile memory devices as shown in
FIG. 1
is limited to the degree to which the active devices can be made smaller in order to increase device packing density and performance. Additionally, the stacked dual gate structure which is formed on the substrate surface is sensitive to process variations of overlaps between the floating gate and the source and drain junctions.
SUMMARY OF THE INVENTION
In accordance with the present invention, a non-volatile semiconductor device for low power applications is fabricated to include a trenched floating gate, a control gate and corner dopings. Embodiments employing the principles of the present invention provide low substrate current programming and an enhanced erase function for high speed operations. Additionally, the device structure of the present invention improves the topography, the scaleability, and the device packing density of the device. Furthermore, embodiments employing the principles of the present invention also minimize the sensitivity to process variations of overlaps between the control gate and the source and drain regions and improve isolation by reducing leakages along the corners of the trench in which the trenched floating gate is formed.
In one embodiment of the present invention, a semiconductor device for low power applications is fabricated on a semiconductor substrate to include a trenched floating gate and corner dopings. The device also includes a p-well junction region and a source and drain region which are formed in the p-well junction region. The trench in which the floating gate is formed partially extends into the p-well junction region and laterally separates the source and drain regions. The depth of the source and drain regions is approximately equal to or less than the depth of the trench. The corner dopings are formed in the semiconductor substrate just below the substrate surface. The corner dopings are immediately contiguous to the upper vertical sides of the trench in which the trenched floating gate is formed and immediately contiguous to the substrate surface.
In accordance with the present invention, a trenched floating gate semiconductor device with corner dopings for low power applications is fabricated by first forming a well junction in the silicon substrate. A trench is then etched in the silicon substrate and the substrate is implanted with dopant impurities to form a channel region beneath the trench. In a preferred embodiment, a depletion type channel region is formed to achieve a low threshold voltage. The depletion type channel region is formed by implanting dopant impurities of the same type as those used for the source and drain regions. A trench-to-gate insulating layer is deposited inside the trench followed by a layer of polysilicon to form the trenched floating gate. The polysilicon layer is planarized and an inter-gate dielectric layer is formed on a top surface of the trenched floating gate. A control gate is then fabricated on the inter-gate dielectric layer. After the control gate has been formed, the substrate is then implanted with dopant impurities to form the corner dopings. Finally, control gate spacers are formed at the vertical surfaces of the control gate, and source and drain regions are implanted into the substrate.
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Advanced Micro Devices , Inc.
Pham Long
Shukla Ravindra B.
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