Trenched gate semiconductor device

Details Trenched gate semiconductor device Trenched gate semiconductor device

1999-08-17

2001-04-10

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000, C257S328000, C257S382000, C257S383000, C257S388000, C257S412000, C257S413000

Reexamination Certificate

active

06215149

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a trench type gate and a fabrication method therefor.
2. Description of the Related Art
As the size and capacity of integrated semiconductor devices increases, the need for a power controlling semiconductor device having a high breakdown voltage, a high current, and high switching characteristics also increases. Such a power controlling semiconductor device should consume less power in a normal operating state and be small.
One commonly used power controlling semiconductor device is a dynamic metal oxide semiconductor field effect transistor (DMOSFET) adopting a general planar diffusion technology. More recently, however, MOSFET devices having a trench type gate in which a semiconductor substrate is etched to a predetermined depth to form a trench have attracted the attention of the industry. The trench is filled with a gate polysilicon.
FIG. 1
is a sectional view of a conventional power MOSFET having a trench type gate. In
FIG. 1
, an N
+
semiconductor substrate
10
is doped with a first conductive type impurity at a high concentration. An N
−
epitaxial layer
12
is formed on the substrate
10
. A P
−
body region
14
is doped with a second conductive type impurity at a low concentration is formed on the N
−
epitaxial layer
12
. An N
+
source region
16
is formed on the P
−
body region
14
. A gate insulating layer
18
is formed on the N
+
source region
16
. A gate
20
fills a trench (not shown). An interlayer dielectric (ILD) film
22
is formed on the gate insulating layer
18
. A source electrode
24
is connected to the N
+
source region
16
. A gate electrode
26
is connected to the trench type gate
20
.
In a conventional device, to reduce signal delay in the gate, the trench is filled with highly doped polysilicon after forming a trench in a semiconductor substrate. Alternatively, after filling the trench with undoped polysilicon, the polysilicon is doped by soaking the device in phosphoryl chloride (POCl
3
) solution or by implanting phosphorous (P) ions into the trench.
According to the conventional method for forming a gate, a large amount of ionized impurities e.g. phosphorous ions, working as positive charges, concentrate on the interface between a gate oxide layer and a polysilicon layer or in the gate oxide layer during its fabrication process. If a negative bias is applied under these conditions, leakage current in the gate oxide layer increases at a low voltage due to the ionized positive ions. This phenomenon occurs mostly in a power MOSFET adopting a thick gate oxide layer having a thickness greater than 300 A. This phenomenon becomes severe as the amount of ions accumulated in the gate oxide layer increases.
In particular, the oxide layer of a power MOSFET adopting a trench type gate thins at the corners of the trench. As a result, leakage current at low voltages increases when a negative bias is applied to a gate electrode thereby considerably lowering the reliability of the gate oxide layer.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device that overcomes the problems associated with prior art semiconductor devices.
It is another object of the present invention to provide a semiconductor device and a fabrication method therefor in which accumulation of ionized impurities in the interface between a gate insulating layer and a gate or in the gate insulating layer is suppressed thereby minimizing leakage current and improving the operating characteristics of the gate insulating layer.
It is yet another object of the present invention to provide a power semiconductor device and a fabrication method therefor capable of withstanding a high voltage.
The semiconductor device having a trench type gate includes a trench formed on a semiconductor substrate and a gate insulating layer formed on the trench. A gate is formed to fill the trench, the gate being insulated from the semiconductor substrate by the gate insulating layer. A barrier layer is formed between the gate insulating layer and the gate for preventing migration of impurities from the gate to the gate insulating layer. The gate is formed of polysilicon doped with impurities and the barrier layer is formed of a refractory metal. The refractory metal is titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), or tungsten (W).
A silicide layer is formed between the gate and the barrier layer for reducing gate resistance. The silicide layer may be formed of a refractory metal, for example, titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), or tungsten (W).
Another embodiment of the present invention is a power semiconductor device having a trench type gate. The power semiconductor device comprises a first conductivity type semiconductor substrate, a second conductivity type body region formed on the substrate, and a first conductivity type source region formed on the body region. A trench is formed through the source and body region. A gate is formed in the trench, the gate being insulated from the substrate by a gate insulating layer. A barrier layer is formed between the gate insulating layer and the gate for preventing migration of impurities from the gate to the gate insulating layer. An interlayer dielectric film is formed on the barrier layer. A gate electrode is connected to the gate via a contact hole formed in the interlayer dielectric film and a source electrode is connected to the source region via a contact hole formed in the interlayer dielectric film.
The gate is formed of polysilicon doped with impurities and the barrier layer is formed of a refractory metal. The refractory metal is titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), or tungsten (W).
A silicide layer is formed between the gate and the barrier layer for reducing gate resistance. The silicide layer may also be formed of a refractory metal, for example, titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), or tungsten (W).
A method for fabricating a semiconductor device having a trench type gate is provided. The method comprises forming a trench in a semiconductor substrate and forming a gate insulating layer on inner walls of the trench and on the semiconductor substrate. The method further comprises forming a barrier layer on the gate insulating layer and forming a gate electrode by filling the trench after forming the barrier layer. Forming the barrier layer includes forming the barrier layer of a refractory metal and wherein forming the gate includes forming the gate of polysilicon doped with impurities. Forming the barrier layer of a refractory metal includes forming the barrier layer of titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), or tungsten (W).
Forming the gate comprises forming a polysilicon layer doped with impurities after forming the barrier layer and forming a silicide layer on the barrier layer by annealing the device after forming the polysilicon layer.
A method for fabricating a power semiconductor device having a trench type gate is provided. The method comprises forming a second conductivity type body region on a first conductivity type semiconductor substrate, forming a first conductivity type source region on the body region, and forming a trench in the semiconductor substrate. The method further comprises forming a gate insulating layer on the semiconductor substrate after forming the trench, forming a barrier layer on the gate insulating layer, and forming a gate by filling the trench after forming the barrier layer. The method also comprises forming an interlayer dielectric film after forming the

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