Trench transistor structure and formation method

Details Trench transistor structure and formation method Trench transistor structure and formation method

2001-11-28

2003-06-03

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S282000

Reexamination Certificate

active

06573143

ABSTRACT:

FIELD OF THE INVENTION
The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a method for forming a trench transistor.
BACKGROUND ART
As semiconductor geometries continue to become smaller and smaller, new approaches arise in the fabrication of the semiconductor devices. One such example is found in “trench transistors”. In a trench transistor, a gate is formed within a trench formed into a substrate. In such trench transistors, as with more conventional transistors, it is desired to create a doping profile which achieves a desired characteristic. Unfortunately, such a doping profile is not easily achieved in a trench transistor.
Specifically, in order to achieve a desired doping profile in a trench transistor, multiple pocket implantations are commonly required. Such multiple pocket implantations are complex and significantly increase the fabrication cost associated with trench transistors. Furthermore, the requirement for multiple pocket implantations increases the number of process steps required to form a trench transistor. As a result, the multiple pocket implantations associated with conventionally fabricated trench transistors reduce throughput, increase cost, decrease yield, and degrade the reliability of the trench transistor formation process.
As yet another drawback, trench transistors, which form the gate in a trench within the substrate, also suffer from deleterious gate to source and/or gate to drain electrical shorting. That is, by forming the gate in a trench in the substrate, instead of as a raised structure residing above the substrate, trench transistors are prone to the aforementioned shorting.
Thus, a need exists for a method to form a trench transistor having an idealized doping profile. Still another need exists for a method which meets the above need and which forms a trench transistor without the complexity and increased cost associated with the multiple pocket implantations conventionally required to form the source and drain regions and the source and drain extension regions. Still another need exists for a method which meets the above needs and which minimizes deleterious gate to source or gate to drain shorts.
SUMMARY OF INVENTION
The present invention provides a method for forming a trench transistor having an idealized doping profile. The present invention further provides a method which achieves the above accomplishment and which forms a trench transistor without the complexity and increased cost associated with the multiple pocket implantations conventionally required to form the source and drain regions and the source and drain extension regions. The present invention also provides a method which achieves the above accomplishments and which minimizes deleterious gate to source or gate to drain shorts.
In one embodiment, the present invention is comprised of a method which includes forming a trench having sidewalls and a bottom into a substrate. The present embodiment also recites forming sidewalls spacer regions along at least a portion of the sidewalls of the trench. Subsequently, the present embodiment forms a gate dielectric along at least a portion of the bottom of the trench, and deposits a gate metal within the trench. The present embodiment then subjects the substrate to an etching process such that the top surface of the substrate is lower than the top surface of the sidewall spacer regions formed along the sidewalls of the trench. The present embodiment then performs a single dopant implantation step which results in the formation of both the source and drain regions and the source and drain extension regions wherein the source and drain regions have an implantation depth which is greater than the implantation depth of the source and drain extension regions. Additionally, substantially no dopant is implanted within a channel region residing beneath the gate metal disposed within the trench. In so doing, an idealized dopant profile is achieved within the trench transistor using the single dopant implantation step.
In yet another embodiment, the present invention includes the steps of the above-described embodiment and further comprises depositing a layer of metal above the semiconductor substrate, and subjecting the layer of metal to an annealing process to form silicided regions within the substrate above at least a portion of the source and drain regions and proximate to the gate metal disposed within the trench. In so doing, a low resistance contact to the source and drain regions is formed.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.


REFERENCES:
patent: 6171914 (2001-01-01), Liao et al.
patent: 2001/0039092 (2001-11-01), Morimoto et al.
patent: 11-154749 (1999-06-01), None

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