Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-02-26
1999-07-13
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438633, 438646, 438926, 438669, 438619, H01L 21469
Patent
active
059240067
ABSTRACT:
A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. A dielectric layer is deposited over the metal lines and dummy metal areas wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines.
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Hsue Chen-Chiu
Lur Water
Wu Hong J.
Everhart Caridad
United Microelectronics Corp.
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