Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-30
2001-03-20
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S424000
Reexamination Certificate
active
06204131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and more particularly, to a trench structure for isolating semiconductor elements and a method for forming the same.
2. Description of the Related Art
There are two basic methods for isolating semiconductor elements on a semiconductor substrate: the LOCOS (localized oxidation of silicon) method, and trench isolation. However, with the increasing complexity and shrinking dimensions of semiconductor devices, trench isolation is emerging as the standard method of isolating semiconductor elements on semiconductor substrates.
FIG. 2
shows a conventional CMOS transistor having a dual-well. The conventional CMOS structure includes a semiconductor substrate
1
in which P and N-wells
7
and
8
are formed, isolation trenches T
1
isolating the P and N-wells
7
and
8
from each other, an N-channel transistor
9
formed on the P-well
7
, and a P-channel transistor
10
formed on the N-well
8
.
In the above described CMOS structure, adjacent transistors have opposite polarities. Thus, current leakage occurring between the adjacent transistors under the isolation trench T
1
is higher than the current leakage expected with a MOS structure, in which adjacent transistors have like polarities. The current leakage between the adjacent transistors causes a latch-up phenomenon to occur and a parasitic transistor to be formed between the adjacent transistors. Therefore, to reduce the current leakage, the surface area of the isolation trench should be increased. The increase in the surface area increases the distance between adjacent source/drain regions of the parasitic transistor, thereby increasing a threshold voltage of the parasitic transistor of the isolation region.
However, the increase in the surface area of the isolation trench results in a lower degree of integration of the semiconductor device due to an increase in its forming area.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems.
In accordance with the invention, a trench structure is provided for isolating semiconductor elements in which both the formation of a parasitic transistor and the occurrence of the latch-up phenomenon can be suppressed, while the degree of integration of the semiconductor element is improved.
In accordance with the invention, a method is provided for forming a trench structure of a semiconductor device in which a CMP process can be easily performed by depositing a thin trench insulating layer to improve yield.
To achieve the above objects, the present invention provides a trench structure for isolating semiconductor elements of a semiconductor substrate. The trench structure includes a trench formed in the semiconductor substrate, the trench having at least two grooves provided at the bottom surface of the trench. An insulating material fills the trench including the grooves. Thus, the surface area of the trench structure is increased due to the grooves.
According to another aspect of the present invention, a method for forming a trench structure for isolating semiconductor elements is provided. A shallow groove pattern is formed on a semiconductor substrate. A portion of the semiconductor substrate where the trench is to be formed surrounding the shallow groove pattern is etched. Thus, the trench is formed having the shallow groove pattern on the bottom of the trench. The trench is filled with an insulating material including the shallow groove pattern.
According to an embodiment of the present invention, the shallow groove pattern is formed on the semiconductor substrate by forming a pad oxide layer on the semiconductor substrate, forming a nitride layer on the pad oxide layer, and depositing a photoresist on the nitride layer. A pattern on the photoresist is formed corresponding to the shallow groove pattern using a mask. A portion of the nitride layer is exposed through the patterned photoresist layer, the a portion corresponding to the shallow groove pattern. The nitride layer and the pad oxide layer are etched using the photoresist as a mask. The photoresist is removed and the semiconductor substrate is etched using the nitride layer as a mask, thereby forming the shallow groove pattern in the semiconductor substrate.
Etching a portion of the semiconductor substrate may be accomplished by removing all of the first photoresist, and next depositing a second photoresist on the nitride layer. A pattern on the second photoresist is formed corresponding to the trench on the second photoresist. The nitride layer and the pad oxide layer are etched using the second photoresist as a mask. The second photoresist is removed and the semiconductor substrate is etched using the nitride layer as a mask, thereby forming the trench having the shallow groove pattern.
Filling the trench with an insulating material may be accomplished by forming an insulating layer on the nitride layer which fills up the trench and the shallow groove pattern. A third photoresist is then deposited on the insulating material. A pattern on the third photoresist is formed such that the insulating material is exposed except for a portion corresponding to the trench. The insulating layer is etched using the third photoresist as a mask. The insulating layer is flattened to be flush with the nitride layer. Lastly, the nitride layer and the pad oxide layer are removed.
REFERENCES:
patent: 5691232 (1997-11-01), Bashir et al.
patent: 5895253 (1999-04-01), Akram
Anam Semiconductor Inc.
Booth Richard
Jones Josetta I.
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