Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Patent
1996-11-21
1999-05-18
Picardat, Kevin
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
438460, H01L21/46
Patent
active
059045485
ABSTRACT:
A method of scribing and separating chips on a semiconductor wafer (21) wherein the wafer (21) is patterned and a pattern of intersecting grooves is etched on a selected surface of the semiconductor wafer (21) in a pattern, preferably in a grid pattern, to define chip areas on that surface. Trenches (27) are then formed in the shape of the pattern and the selected surface is adhered to a tape (29). Light is then passed through the tape (29) and semiconductor wafer (21) from the pattern and a pattern of intersecting saw cuts or grooves (28) aligned with the light passing through the wafer (21) is formed. The saw cuts (28) extend from a surface of the wafer (21) opposing the selected surface and are aligned with the pattern of intersecting trenches (27).
REFERENCES:
patent: 4534804 (1985-08-01), Cade
patent: 4604161 (1986-08-01), Araghi
patent: 4961821 (1990-10-01), Drake et al.
patent: 5128282 (1992-07-01), Ormond et al.
patent: 5196378 (1993-03-01), Bean et al.
patent: 5219796 (1993-06-01), Quinn et al.
patent: 5272114 (1993-12-01), van Berkum et al.
patent: 5284792 (1994-02-01), Forster et al.
patent: 5350704 (1994-09-01), Anderson et al.
patent: 5369060 (1994-11-01), Baumann et al.
patent: 5418190 (1995-05-01), Cholewa et al.
Brady III Wade James
Donaldson Richard L.
Picardat Kevin
Stewart Alan K.
Texas Instruments Incorporated
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