Trench power MOSFET fabrication using inside/outside spacers

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S243000, C438S244000, C438S245000, C438S246000, C438S248000, C438S259000, C438S386000, C438S388000, C438S391000, C438S222000, C257S333000, C257S353000, C257SE21546, C257SE21548, C257SE21549, C257SE21550, C257SE21551

Reexamination Certificate

active

07390717

ABSTRACT:
A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

REFERENCES:
patent: 5563085 (1996-10-01), Kohyama
patent: 6538280 (2003-03-01), Nakamura
patent: 6667227 (2003-12-01), Liu et al.
patent: 7060567 (2006-06-01), Hsu
patent: 7160789 (2007-01-01), Park
patent: 2006/0160298 (2006-07-01), Kwon et al.
patent: 2007/0037341 (2007-02-01), Rueger et al.
A Novel Technique for Fabricating High Reliaboe Trench DMOSFETs Using Self-Align Technique and Hydrogen Annealing, Jongdae Kim et al., IEEE Transactions on Electron Devices, vol. 50, No. 2, Feb. 2003.

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