Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-15
2004-01-06
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S332000, C257S333000, C428S208000
Reexamination Certificate
active
06674124
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to microelectronic circuits, and more particularly to trench MOSFET devices having low gate charge.
BACKGROUND OF THE INVENTION
Metal oxide semiconductor field effect transistor (MOSFET) devices that use trench gates provide low turn-on resistance. In such trench MOSFET devices, the channels are arranged in a vertical manner, instead of horizontally as in most planar configurations. Such transistors provide high current per unit area where low forward voltage drops are required.
FIG. 1
shows a partial cross-sectional view of a trench MOSFET device containing an N+ substrate
1
, an N− epitaxial layer
2
, P body regions
3
, and N+ regions
11
. Typically, the P body regions
3
are diffused into the N− epitaxial layer
2
, which is disposed on the N+ substrate
1
, and the N+ regions
11
are in turn diffused in the body regions
3
. Due to the use of these two diffusion steps, a transistor of this type is commonly referred to as a double-diffused metal oxide semiconductor field effect transistor with trench gating or, in brief, a “trench DMOS”.
The trench MOSFET device shown in
FIG. 1
also includes a trench
8
filled with conductive material
10
, which is separated from regions
2
,
3
,
11
by an oxide region
15
,
16
. As arranged, the conductive and insulating materials
10
and
16
in the trench
8
form the gate and gate oxide layer, respectively, of the trench MOSFET. The N+ regions
11
form the sources for the device, and the epitaxial layer
2
and N+ substrate
1
together form the drain of the trench MOSFET device. When a potential difference is applied across the P body
3
and the gate
10
, charges are capacitively induced within the body region
3
, resulting in the formation of a channel within the P body region
3
of the trench MOSFET device adjacent the trench
8
. When another potential difference is applied across the sources
11
and the drain
1
,
2
, a current flows from the source metal
14
to the drain
1
,
2
through the channel, and the trench MOSFET device is said to be in the power-on state.
Examples of trench MOSFET transistors are disclosed, for example, in U.S. Pat. Nos. 5,907,776, 5,072,266, 5,541,425, and 5,866,931, the entire disclosures of which are hereby incorporated by reference.
A typical MOSFET device includes numerous individual MOSFET transistor cells that are fabricated in parallel within a single chip (i.e., a section of a semiconductor wafer). Hence, a chip like that shown in
FIG. 1
typically contains numerous cells. Square-shaped and hexagonal cell configurations are common. In a design like that shown in
FIG. 1
, the substrate region
1
acts as a common drain contact for all of the individual MOSFET transistor cells. All the sources
11
for the MOSFET cells are typically shorted together via a metal source contact
14
that is disposed on top of the N+ source regions
11
. An insulating region
12
, such as borophosphosilicate glass, is typically placed between the conductive material
10
in the trenches
8
and the metal source contact
14
to prevent the gates
10
from being shorted with the source regions
11
. Consequently, to make contact with the gates
10
, the conductive material within the trenches is typically extended into a termination region beyond the MOSFET cells, where a metal gate contact is provided. Since the conductive regions are interconnected with one another via the trenches, this arrangement provides a single gate contact for all the gate regions of the device. As a result of this scheme, even though the chip contains a matrix of individual transistor cells, these cells behave as a single large transistor.
Demand persists for trench MOSFET devices having ever-lower on-resistance. The simplest way to reduce on-resistance is to increase cell density. Unfortunately, the gate charges associated with trench MOSFET devices increase when cell density is increased. The device of
FIG. 1
is disclosed in JP05335582 to Omron Corp. and entitled “Vertical MOSFET device and Manufacture thereof”, the complete disclosure of which is hereby incorporated by reference. This device takes advantage of the fact that oxide film at the trench sidewall forms the channel within the P-body region
3
, while oxide film at the bottom of the trench does not contribute significantly to channel formation, but nonetheless contributes to gate charges. In response, the oxide film
15
at the bottom of the trench
8
can be thickened substantially relative to the oxide film
16
at the sidewall to reduce gate charges. According to the JP05335582 abstract, the thick gate oxide film
15
is formed at the bottom of the groove by stacking oxide films by decompressed CVD until the trench
8
flattens, and etching back this oxide film to form the thick oxide film
15
at the bottom of the trench
8
. Subsequently the thinner gate oxide film
16
is formed at the sidewall of the trench
8
by thermal oxidation.
SUMMARY OF THE INVENTION
Unfortunately, a gate oxide formed by CVD, such as that described in the JP05335582 abstract, creates a high state charge at the interface between the CVD gate oxide and the silicon. This and other disadvantages of the devices of the prior art are addressed by the design and manufacture of the trench MOSFET devices of the present invention.
According to an embodiment of the invention, a trench MOSFET device is provided, which comprises: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench lower and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment. Moreover, those portions of the oxide region that form interfaces with the silicon are thermally grown.
According another embodiment of the invention, a trench MOSFET device is provided which comprises: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and extends through the body region; (e) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (f) a conductive region within the trench adjacent the oxide region; and (g) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. In this embodiment, the lower segment of the oxide region is thicker than the upper segments of the oxide region, establishing shoulders in the oxide region that are adjacent the conductive region along the trench sidewalls.
In some embodiments, the lower segment of the oxide region includes a thermally grown portion (which can range, for example, from 500 to 2000 Angstroms in thickness) adjacent the trench and a
Hshieh Fwu-Iuan
So Koon Chong
Cao Phat X.
General Semiconductor Inc.
Le Thao X.
Mayer Fortkort & Williams PC
Meyer, Esq. Stuart H.
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