Trench isolation method in flash memory device

Details Trench isolation method in flash memory device Trench isolation method in flash memory device

2007-08-21

2007-08-21

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S424000, C438S221000, C438S425000, C438S427000, C438S430000, C438S431000, C438S429000, C438S432000

Reexamination Certificate

active

11019302

ABSTRACT:
The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.

REFERENCES:
patent: 6074931 (2000-06-01), Chang et al.
patent: 6806163 (2004-10-01), Wu et al.
patent: 6964905 (2005-11-01), Inoue
patent: 6974755 (2005-12-01), Ko et al.
patent: 2004/0106256 (2004-06-01), Dong et al.

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