Trench isolation method

Details Trench isolation method Trench isolation method

1997-11-25

2000-12-26

Fourson, George

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438424, 438738, 438743, H01L 21762

Patent

active

061658537

ABSTRACT:
A method of forming trench isolated integrated circuitry on a substrate provides a substrate having a first insulating material within and projecting from an isolation trench and a second insulating material laterally proximate the first insulating material. The second insulating material is etched substantially selective relative to the first insulating material to expose substrate beneath the second insulating material. After the etching, a gate dielectric layer is formed over the exposed substrate. A transistor gate is formed over the gate dielectric layer. In but one other implementation, an oxide layer is thermally grown over a semiconductive substrate. An isolation trench is formed through the thermal oxide layer and the semiconductive substrate. Oxide is deposited within the trenches and formed to project outwardly relative to the thermal oxide. The thermally grown oxide is etched substantially selective relative to the deposited oxide to outwardly expose the semiconductive substrate and provide deposited oxide within the isolation trench which projects outwardly of the substrate. The semiconductive substrate and projecting deposited oxide have an interface therebetween which is substantially void of any recess of the deposited oxide below the semiconductive substrate. After the etching, gate oxide is grown over the substrate and the interface. A transistor gate is formed over the gate oxide over the semiconductive substrate.

REFERENCES:
patent: 4127437 (1978-11-01), Bersin et al.
patent: 4749440 (1988-06-01), Blackwood et al.
patent: 5022961 (1991-06-01), Izumi et al.
patent: 5234540 (1993-08-01), Grant et al.
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5376233 (1994-12-01), Man
patent: 5438012 (1995-08-01), Kamiyama
patent: 5571375 (1996-11-01), Izumi et al.
patent: 5677229 (1997-10-01), Morita et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5731241 (1998-03-01), Jang et al.
patent: 5763315 (1998-06-01), Benedict et al.
patent: 5783495 (1998-07-01), Li et al.
patent: 5795811 (1998-08-01), Kim et al.
patent: 5858858 (1999-01-01), Park et al.
Jensen et al., BPSG to Thermal Oxide Etch Selectivity for Contact Clean Applications, Technical Report DC/DE, Jan. 29, 1991, 9 pages.
Chen, C., et al., "A Novel 0.25 .mu.m Shallow Trench Isolation Technology", United Microelectronics Corp., Advanced Technology Development Dept., Taiwan, R.O.C.; 4 pages (undated).
Wolf, S., et al., "Silicon Processing for the VLSI Era: vol. 1, Process Technology", Lattice Press, pp. 533, 534, 555 1986.

Affiliated with

Also associated with

Rating

Trench isolation method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trench isolation method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench isolation method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-994048