Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-01-27
2001-08-14
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S524000, C438S700000, C257S330000
Reexamination Certificate
active
06274437
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of forming a doped trench as part of the fabrication of a semiconductor device.
DESCRIPTION OF RELATED ART
A first conventional method of forming a doped trench is to implant a semiconductor with a suitable dopant and then etching through the implanted region to leave a trench with two side lobes. This method results in a doping profile as shown in the graph of FIG.
13
. It can be seen from
FIG. 13
that this doping method is characterised by a gradual drop off in concentration in both directions. This method has the disadvantage that the bottom of the doped region generally will not align with the electrode material which is added to the trench at a later stage.
U.S. Pat. 4,415,371 describes a second conventional method of fabricating a sub-micron dimension NPN lateral transistor. An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide field trenches which are utilized to dope the substrate within the action region. n+ regions are implanted in the trench by ion implanting at a large angle. The angle of the ion beams relative to the trench direction ensures that the n+ implanting does not extend to the full depth of the trench. This is due to a shadowing effect.
A disadvantage of this device is that the large ion implanting angle (which is necessary to ensure that the trenches are not fully doped) is non-standard and expensive, and also ionic reflections will reduce the effectiveness of the shadowing. Also the doped region will generally not align with the top of the electrode material which is deposited at a later stage.
SUMMARY OF THE INVENTION
In accordance with the present invention we provide a method of forming a doped trench as part of the fabrication of a semiconductor device, the method comprising:
(i) forming a trench in a semiconductor substrate using a mask to define the trench region;
(ii) either
a) filling the trench and removing part of the contents of the trench to leave a partially filled trench; or
b) partially filling the trench; and
(iii) doping the side walls of the trench with the mask still in place.
The trench may be filled in step (ii) with any suitable material, depending on the particular type of semiconductor device being fabricated. Typically the trench is filled with a suitable electrode material or combination of materials as in a silicided gate.
The trench may be fully or partially filled with electrode material in step (ii) a), and then removed down to a desired level in the trench eg. by etching. Alternatively the trench may be partially filled in one step (ii) b) up to the desired level. In this case the trench is typically partially filled by evaporation of eg. aluminium.
The lateral spread of the doping profile can be accurately controlled and can be made to be very narrow. This is highly advantageous where trenches must be placed adjacent and as close as possible to one another and allows a particularly high device density. Conventional transistor arrays exhibit a device density of the order of 4 million devices per square inch. The present invention can be utilised to form a transistor array with approximately 400 million devices per square inch.
Device parameters such as the particular electrode material used and the dopant ions/atoms will depend on the particular device being fabricated. Typically the electrode is polysilicon or any refractory metal. Typically the dopant atoms are arsenic, phosphorous, boron or antimony for silicon, but other elements will be used for other substrate materials.
Preferably the trench is partially filled before the doping step. This ensures that the bottom of the doping profile is self-aligned to the top of the trench filling material (trench refill). Where the trench refill acts as an electrode in the final device, this will help to minimise the capacitance between this electrode and the doping region, and ensures channel continuity in a MOS gated device.
Where the gate is principally polysilicon, the doping step (iii) will also dope the polysilicon. This will enhance the electrode conductivity and therefore its switching speed.
Typically (as in a MOSFET but not in a device such as a MESFET) a dielectric (such as silicon dioxide) will be formed on the surface of the trench between steps (i) and (ii). After step (ii) the dielectric at the upper part of the trench will be exposed. The doping step may then be carried out by penetrating through this layer or alternatively, the exposed dielectric material may be removed beforehand.
Typically, the doping step (iii) comprises introducing dopant ions from an angled ionic source. This can result in very high surface dopant concentrations. This allows very low sheet resistivity regions to be formed. Further, the use of ion implantation means that a rapid thermal anneal can be used which will mean that if the semiconductor device is a power device which is used in a smart power device (where there are other impurity profiles in logic circuits) then this process will be more suitable as it will not affect the previous processing.
The angled implanting step may be carried out with a low angle of implant. This generally means that more than one implanting step could be required to dope all sides of the trench. Alternatively the angle of the ionic source to the surface of the substrate may be increased. The resulting ionic reflections from the side walls of the trench then causes substantially all sides of the trench to be at least partially doped and generally only one implanting step could be required.
Alternatively, the doping step (iii) may comprise diffusing dopant ions into the sidewalls of the trench from a dopant gas such as arsenic, phosphorous, boron, antimony or any other suitable dopant gas.
Further alternatives for the doping step (iii) include deposition of a dopant source such as heavily doped glass; and filling the exposed part of the trench with spin on dopant. Where the dopant mechanism is from a dielectric source (such as spin on glass or doped silicon dioxide), the material can be conveniently etched back to planarise the trench.
The resulting doped trench can then be utilised in the production of a wide variety of semiconductor devices. Examples of such devices are a trench gated power device such as a power MOSFET, MESFET or a power IGBT, a logic transistor or a memory cell.
The mask which is used to define the trench etch is also used to define the doping area in step (iii). This allows the doping step to be carried out by a variety of techniques such as ion implantation or gaseous diffusion, and any choice of doping (impurity) atoms. A further advantage of using the mask in both steps is that in the field areas (i.e. areas that do not have n+ source regions and where the gate contact will be made) this mask is desirable as it reduces the gate capacitance.
The present invention also extends to a device which has been constructed according to the previously described method. The device typically includes doped regions of the side walls of the trench which have a doping concentration which is substantially uniform in the exposed part of the trench (i.e. the part which is not masked by electrode material after step (ii)). The doped region also typically has a well defined drop-off in concentration at the top of the electrode material.
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Blank Rome Comisky & McCauley LLP
Chaudhuri Olik
Eaton Kurt
Totem Semiconductor Limited
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