Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-26
2003-03-18
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S212000, C438S259000, C438S589000, C438S700000
Reexamination Certificate
active
06534367
ABSTRACT:
This invention relates to trench-gate semiconductor devices, for example power MOSFETs (insulated-gate field-effect transistors), and to their manufacture using self-aligned techniques to fabricate the devices with compact geometries.
Trench-gate semiconductor devices are known, having a trench-gate in a trench that extends from a source region through a channel-accommodating region to a drain region of the first conductivity type. United States patent specification U.S. Pat. No. 6,087,224 (our reference PHB34245) discloses an advantageous method of manufacturing such trench-gate semiconductor devices, wherein:
(a) a narrow window is defined by providing sidewall extensions at the sidewalls of a wider window in a first mask at a surface of a semiconductor body,
(b) a trench is etched into the body at the narrow window, and the gate is provided in the trench,
(c) the source region is provided so as to be self-aligned with the trench-gate by means of the sidewall extensions, and
(d) an insulating overlayer is provided over the trench-gate.
This method permits the use of self-aligned masking techniques in a flexible device process with good reproducibility. In particular, by using the sidewall extensions in different stages, narrow trench-gates can be formed and the source region and a contact window for a source electrode can be determined in a self-aligned manner with respect to this narrow trench. The whole contents of U.S. Pat. No. 6,087,224 are hereby incorporated herein as reference material.
U.S. Pat. No. 6,087,224 discloses various forms of the method. Thus, for example, the source region and/or channel-accommodating region may be provided either before or after forming the trench-gate, either a deep or shallow more highly-doped region may be provided (also in a self-aligned manner) in the channel-accommodating region, either a doped-semiconductor or a metal or silicide material may be used for the gate, and either an oxidized or deposited insulating overlayer may be provided (also in a self-aligned manner) over the trench-gate. In the detailed embodiments described, the insulating overlayer is provided in the presence of the sidewall extensions and is constrained by these sidewall extensions. Furthermore, when the sidewall extensions are removed to form doping windows for forming the source region, the doping is constrained by the simultaneous presence of both the first mask part and the previously-provided overlayer over the trench-gate,
It is an aim of the present invention to provide a modification of such a method, involving a novel sequence of process steps that can simplify and improve the provision of the insulating overlayer and that can provide other advantageous device features in relation thereto.
According to the present invention, there is provided such a method of manufacturing a trench-gate semiconductor device, for example an insulated-gate field-effect device, wherein:
(a) a narrow window is defined by providing sidewall extensions at the sidewalls of a wider window in a first mask at a surface of a semiconductor body,
(b) a trench is etched into the body at the narrow window, and the gate is provided in the trench,
(c) the source region is provided so as to adjoin a sidewall of the trench (and is preferably self-aligned with the trench-gate by means of the sidewall extensions), and
(d) an insulating overlayer is provided over the trench-gate using the following sequence of steps:
removing the sidewall extensions to leave at least a part of the first mask with the wider window at the surface of the body,
depositing insulating material to a thickness that is sufficient to fill the wider window and to extend above the wider window and over the first mask part,
etching back the insulating material to leave the insulating overlayer in the wider window in the first mask part,
and then removing the first mask part before providing a source electrode to contact the source region and an adjacent surface region of the body and to extend over the insulating overlayer over the trench-gate.
The present inventors find that (after etching the trench and providing the trench-gate) the edge quality of the wider window in the first mask part is better than that of the sidewall extensions and that its re-exposure (by removing the sidewall extensions) permits the insulating overlayer to be provided in a reproducible manner by a simple deposition and etch-back process that fills this wider window. Thus, whereas the edge of the sidewall extensions is typically tapered and possibly irregular in etch-back, the first mask part can have a well-defined vertical edge. The profile of this well-defined vertical edge can be reproducibly transferred, in accordance with the invention, to the edge of the contact window formed in the insulating overlayer by removal of the first mask part. The resulting edge of the insulating overlayer can be used in various ways, as described hereinafter. Furthermore, the formation of the insulating overlayer is not constrained by the presence of the sidewall extensions, because these sidewall extensions have been removed.
Because the insulating overlayer is formed filling the wider window of the first mask part, it extends a well-defined lateral distance onto the adjacent body surface from over the trench-gate. As such, there is a well-defined, reproduceable spacing between the sidewall of the trench and the edge of the contact window that is formed in the insulating overlayer by removal of the first mask part. This well-defined, reproduceable spacing provides a good safeguard against short-circuiting of the source electrode to the trench-gate at the edge of the contact window. Furthermore, the resulting insulating overlayer can readily be formed over a slightly sunken trench-gate such that it also extends inside an upper part of the gate trench. In this way, reliable insulation can be provided over the top corner of the gate trench to avoid short-circuits.
Furthermore, the process sequence in accordance with the invention opens up opportunities for providing the source region doping at stages in which the doping process is not constrained by the simultaneous presence of both the first mask part and the previously-provided overlayer over the trench-gate.
Thus, the source region is advantageously provided using the following sequence of steps before depositing the insulating material for the insulating overlayer:
removing the sidewall extensions to leave at least a part of the first mask with the wider window at the surface of the body and to form within the wider window a doping window between the first mask part and the trench-gate, and
introducing dopant of a first conductivity type into the body via the wider window (that includes this doping window) so as to form the source region adjacent to the trench-gate.
Other alternative process sequences are also possible for providing the source region (or at least its doping) before depositing the insulating material for the insulating overlayer. Thus, the source region may be implanted at the wider widow in the first mask part before providing the sidewall extensions, or its doping may be implanted as a layer at the body surface before providing the first mask. However, in both these cases the trench is then etched through the source region doping, which is less advantageous (as described below).
Depending on how other features of the device are formed, the full extent of the insulating overlayer defined by the filling of the wider window may be retained in the manufactured device. However, it may be modified in subsequent processing. Thus, for example, after removing the first mask part in stage (d) and before providing the source electrode, the insulating material of the insulating overlayer may be isotropically etched back a sufficient distance to increase the area of the source region not covered by the insulating overlayer.
Methods in accordance with the present invention are particularly beneficial for manufacturing compact cellular devices, such as power MOSFETs. Thus, the first mask and its associ
Farr Robert J.
Forbes Peter J.
Grover Raymond J.
Peake Steven T.
Petkos Georgios
Biren Steven R.
Chaudhuri Olik
Garcia Joannie Adelle
Koninklijke Philips Electronics , N.V.
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