Trench-free buried contact

Details Trench-free buried contact Trench-free buried contact

2000-05-26

2001-08-07

Bowers, Charles (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S383000, C257S384000, C438S238000, C438S586000, C438S655000, C438S657000

Reexamination Certificate

active

06271570

ABSTRACT:

RELATED PATENT APPLICATION
U.S. patent application Ser. No. 09/035,139 to K. C. Huang et al.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an improved buried contact without a trench in the fabrication of integrated circuits.
(2) Description of the Prior Art
FIGS. 1-3
illustrate the typical buried contact process of the prior art.
FIG. 1
illustrates a partially completed integrated circuit device. Field oxide regions, such as
12
, are formed in and on the semiconductor substrate
10
. A gate oxide layer
14
is grown upon the surface of the substrate. Typically, a so-called “split poly” process is used wherein a first layer of polysilicon
16
is deposited over the gate oxide layer to protect the gate oxide from the photoresist process. A layer of photoresist is coated over the polysilicon layer
16
and patterned to form the photoresist mask
20
.
The polysilicon and gate oxide layers are etched away where they are not covered by the photoresist mask to form an opening where the buried contact is to be formed. As illustrated in
FIG. 2
, the second layer of the split poly
22
is deposited over the first polysilicon layer and within the opening. A second photoresist mask
24
is formed over the substrate.
Referring now to
FIG. 3
, dopant from the polysilicon layer
22
is driven in to form the buried contact
26
and the polysilicon and gate oxide layers are etched to form gate electrode
28
and polysilicon interconnection line
30
. Source/drain regions
32
are formed.
As device dimensions and cell size continue to decrease for high density and improved performance in integrated circuits, there is a growing demand for lower junction leakage and lower contact resistance. However, the contact resistance and junction leakage will increase in the conventional buried contact process if there is misalignment of the photoresist mask during polysilicon etching.
FIG. 4
illustrates the case in which the photoresist mask
24
is shifted to the left. Buried contact trench
35
is formed. This causes an increase in both contact resistance and leakage current.
FIG. 5
illustrates the case in which the photoresist mask is shifted to the right. A disconnection gap
37
is left between the buried contact
26
and the source/drain region
32
. This increases contact resistance by causing a high series resistance. The dotted lines in each figure illustrates the current path.
A number of patents disclose methods for improving a device in which a buried contact trench has been formed. For example, U.S. Pat. No. 5,525,552 to J. M. Huang teaches the use of a low dielectric constant spacer to provide better immunity of the buried contact trench. U.S. Pat. No. 5,607,881 also to J. M. Huang teaches linking the buried contact junction and the source junction by an extra high dosage N+ implant to overcome the disadvantages of a buried contact trench. U.S. Pat. No. 5,668,051 to Chen et al teaches a thin polysilicon layer within the buried contact trench. U.S. Pat. No. 5,652,152 to Pan et al discloses the use of a PSG spacer to solve the buried contact trench problem.
Other patents teach methods to avoid forming a buried contact trench. For example, U.S. Pat. No. 5,494,848 to H. W. Chin teaches the use of a reverse tone oversized buried contact mask to prevent formation of a buried contact trench. U.S. Pat. No. 5,654,231 to M. S. Liang et al teaches the use of sidewall spacers to prevent the formation of a buried contact trench in DRAM technology. Co-pending U.S. patent application Ser. No. 09/035,139 to K. C. Huang et al teach a method of forming polysilicon gate electrodes and interconnection lines before forming a buried contact and depositing a refractory material layer over the buried contact.
Still other patents teach other buried contact processes. For example, U.S. Pat. No. 5,332,913 to Shappir discloses a buried interconnect structure in which a contact is formed over a field oxide region. A poly-epi silicon layer is formed over the contact and another oxidation region is formed over the poly-epi silicon layer. U.S. Pat. No. 5,543,362 to Wu teaches a process in which a silicide layer is deposited over the buried contact region followed by a polysilicon layer and topped with a second silicide layer. U.S. Pat. No. 5,162,259 to Kolar et al teaches forming a silicide over the buried contact region and depositing polysilicon overlying the silicide.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of forming buried contact junctions.
Another object of the present invention is to provide a method of forming buried contact junctions which avoids the formation of a trench caused by mask misalignment.
Another object of the invention is to provide a method of forming buried contact junctions which avoids the formation of a disconnection gap caused by mask misalignment.
Yet another object of the present invention is to provide a method of forming buried contact junctions in which only a single deposition of polysilicon is required.
A further object of the invention is to provide a method of forming buried contact junctions in which a selective tungsten process is used to form the polycide gate and interconnection lines.
A still further object is to provide a method of forming buried contact junctions which avoids the formation of a trench caused by mask misalignment and in which only a single deposition of polysilicon is required.
A still further object is to provide a method of forming buried contact junctions which avoids the formation of a trench caused by mask misalignment, in which only a single deposition of polysilicon is required, and in which a selective tungsten process is used to form the polycide gate and interconnection lines.
In accordance with the objects of this invention a new method of forming an improved buried contact junction is achieved. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a hard mask layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
Also, in accordance with the objects of this invention, a new integrated circuit device having a buried contact junction is described. A buried contact junction lies within a semiconductor substrate having a titanium silicide layer thereover and a tungsten contact layer overlying the titanium silicide. A polycide gate electrode lies on the surface of the semiconductor substrate having source and drain regions within the semiconductor substrate surrounding the polycide gate electrode wherein one of the source and drain regions contacts the buried contact junction. An insulating layer overlies the said polycide gate electrode, the tungsten contact layer, and the source and drain regions. A patterned conducting layer overlies the

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