Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-06-04
1999-11-09
Booth, Richard A.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
H01L 21336
Patent
active
059813440
ABSTRACT:
To reduce susceptibility to punchthrough, the channel region of the P body region of a trench field effect transistor is formed in a layer of lightly doped epitaxial silicon. As a result, the channel region has less counterdoping from the background epitaxial silicon and has a greater net P type dopant concentration. Due to the higher net dopant concentration of the P body region, the depletion regions on either side of the P body region expand less far inward through the P body region at a given voltage, thereby rendering the transistor less susceptible to source-to-drain punchthrough. To maintain a low R.sub.DSon, the relatively high conductivity of an accumulation region formed along a sidewall of the trench of the transistor when the transistor is on is used to form a conductive path from the channel region to an underlying relatively highly conductive layer upon which the lightly doped epitaxial layer is formed. This underlying relatively highly conductive layer may, for example, be either substrate or a more highly doped epitaxial silicon layer.
REFERENCES:
patent: 4078947 (1978-03-01), Johnson et al.
patent: 4376286 (1983-03-01), Lidow et al.
patent: 4593302 (1986-06-01), Lidow et al.
patent: 4642666 (1987-02-01), Lidow et al.
patent: 4680853 (1987-07-01), Lidow et al.
patent: 4705759 (1987-11-01), Lidow et al.
patent: 4803532 (1989-02-01), Mihara
patent: 4893160 (1990-01-01), Blanchard
patent: 4941026 (1990-07-01), Temple
patent: 4959699 (1990-09-01), Lidow et al.
patent: 5008725 (1991-04-01), Lidow et al.
patent: 5016066 (1991-05-01), Takahashi
patent: 5017504 (1991-05-01), Nishimura et al.
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5138422 (1992-08-01), Fujii et al.
patent: 5168331 (1992-12-01), Yilmaz
patent: 5387528 (1995-02-01), Hutchings et al.
patent: 5405794 (1995-04-01), Kim
patent: 5473176 (1995-12-01), Kakumoto
patent: 5474943 (1995-12-01), Hshieh et al.
patent: 5479037 (1995-12-01), Hshieh et al.
patent: 5514608 (1996-05-01), Williams et al.
patent: 5532179 (1996-07-01), Chang et al.
Wolf, S. and Tauber, R., Silicon Processing for the VLSI Era, vol. 1: Process Technology, pp. 124-160, Lattice Press (1986).
Wolf, S., Silicon Processing for the VLSI Era, vol. 2: Process Integration, pp. 674-675 Lattice Press (1990).
Syau, T. et al., "Comparison of Ultralow Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's," IEEE Transactions on Electron Devices 41:800-808 (May 1994).
Chang Mike F.
Hshieh Fwu-Iuan
Booth Richard A.
Klivans Norman R.
Siliconix incorporated
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